公开(公告)号：US20110235444A1

公开(公告)日：2011-09-29

申请号：US13070977

申请日：2011-03-24

申请人： Ching-Te Chuang ,  Wei-Chiang Shih ,  Hung-Yu Lee ,  Jihi-Yu Lin ,  Ming-Hsien Tu ,  Shyh-Jye Jou ,  Kun-Di Lee

发明人： Ching-Te Chuang ,  Wei-Chiang Shih ,  Hung-Yu Lee ,  Jihi-Yu Lin ,  Ming-Hsien Tu ,  Shyh-Jye Jou ,  Kun-Di Lee

IPC分类号： G11C7/00

CPC分类号： G11C11/413

摘要： SRAM writing system and related apparatus are provided. The writing system of the invention has a dummy replica writing circuit, a negative pulse controller and at least a normal writing circuit; each normal writing circuit includes a write driver and a negative pulse supplier. While writing, the dummy replica writing circuit drives a dummy replica bit-line, such that the negative pulse controller generates a negative pulse control signal according to level of the dummy replica bit-line. In each writing circuit, when the write driver conducts to connect an associated bit-line to a bias end for driving a level transition, the negative pulse supplier switches the bias end from an operation voltage to a different negative pulse voltage according to the received negative pulse control signal.

摘要翻译： 提供SRAM写入系统及相关装置。 本发明的写入系统具有虚拟副本写入电路，负脉冲控制器和至少一个正常写入电路; 每个正常写入电路包括写入驱动器和负脉冲供应器。 在写入时，虚拟副本写入电路驱动虚拟副本位线，使得负脉冲控制器根据虚拟副本位线的电平产生负脉冲控制信号。 在每个写入电路中，当写入驱动器将相关联的位线连接到用于驱动电平转换的偏置端时，负脉冲供应器根据接收到的负值将偏置端从工作电压切换到不同的负脉冲电压 脉冲控制信号。

公开(公告)号：US07492628B2

公开(公告)日：2009-02-17

申请号：US11933505

申请日：2007-11-01

申请人： Ching-Te Chuang ,  Jae-Joon Kim ,  Keunwoo Kim

发明人： Ching-Te Chuang ,  Jae-Joon Kim ,  Keunwoo Kim

IPC分类号： G11C11/00

CPC分类号： G11C11/412 ,  G11C11/413

摘要： Techniques are provided for a computer-readable medium encoding a memory using a back-gate controlled asymmetrical memory cell. In one aspect, the cell includes five transistors and can be employed for static random access memory (SRAM) applications. An encoded inventive memory circuit can include a plurality of bit line structures, a plurality of word line structures that intersect the plurality of bit line structures to form a plurality of cell locations, and a plurality of cells located at the plurality of cell locations. Each cell can be selectively coupled to a corresponding one of the bit line structures under control of a corresponding one of the word line structures. Each cell can include a first inverter having first and second field effect transistors (FETS) and a second inverter with third and fourth FETS that is cross-coupled to the first inverter to form a storage flip-flop. One of the FETS in the first inverter can be configured with independent front and back gates and can function as both an access transistor and part of one of the inverters.

摘要翻译： 为使用背栅控制的非对称存储单元编码存储器的计算机可读介质提供技术。 在一个方面，电池包括五个晶体管，并且可以用于静态随机存取存储器（SRAM）应用。 编码的本发明的存储器电路可以包括多个位线结构，与多个位线结构相交以形成多个单元位置的多个字线结构以及位于多个单元位置的多个单元。 每个单元可以在对应的一个字线结构的控制下选择性地耦合到相应的一个位线结构。 每个单元可以包括具有第一和第二场效应晶体管（FETS）的第一反相器和具有与第一反相器交叉耦合以形成存储触发器的第三和第四FET的第二反相器。 第一反相器中的FETS之一可以配置有独立的前门和后门，并且可以用作存取晶体管和其中一个逆变器的一部分。

公开(公告)号：US20080278992A1

公开(公告)日：2008-11-13

申请号：US12140366

申请日：2008-06-17

申请人： Ching-Te Chuang ,  Jae-Joon Kim ,  Keunwoo Kim

发明人： Ching-Te Chuang ,  Jae-Joon Kim ,  Keunwoo Kim

IPC分类号： G11C11/00

CPC分类号： G11C11/412

摘要： Techniques are provided for employing independent gate control in asymmetrical memory cells. A memory circuit, such as an SRAM circuit, can include a number of bit line structures, a number of word line structures that intersect the bit line structures to form a number of cell locations, and a number of asymmetrical memory cells located at the cell locations. Each of the asymmetrical cells can be selectively coupled to a corresponding one of the bit line structures under control of a corresponding one of the word line structures. Each of the cells can include a number of field effect transistors (FETS), and at least one of the FETS can be configured with separately biased front and back gates. One gate can be biased separately from the other gate in a predetermined manner to enhance read stability of the asymmetrical cell.

摘要翻译： 提供了在不对称存储单元中采用独立门控制的技术。 诸如SRAM电路的存储器电路可以包括多个位线结构，与位线结构相交以形成多个单元位置的多个字线结构以及位于单元的多个非对称存储单元 位置。 每个非对称单元可以在相应的一个字线结构的控制下选择性地耦合到位线结构中的对应的一个。 每个单元可以包括多个场效应晶体管（FETS），并且FETS中的至少一个可以被配置为单独偏置的前门和后门。 一个栅极可以以预定的方式与另一个栅极分开偏置，以增强不对称单元的读取稳定性。

公开(公告)号：US07417889B2

公开(公告)日：2008-08-26

申请号：US11362612

申请日：2006-02-27

申请人： Ching-Te Chuang ,  Jae-Joon Kim ,  Keunwoo Kim

发明人： Ching-Te Chuang ,  Jae-Joon Kim ,  Keunwoo Kim

IPC分类号： G11C11/00

CPC分类号： G11C11/412

摘要： Techniques are provided for employing independent gate control in asymmetrical memory cells. A memory circuit, such as an SRAM circuit, can include a number of bit line structures, a number of word line structures that intersect the bit line structures to form a number of cell locations, and a number of asymmetrical memory cells located at the cell locations. Each of the asymmetrical cells can be selectively coupled to a corresponding one of the bit line structures under control of a corresponding one of the word line structures. Each of the cells can include a number of field effect transistors (FETS), and at least one of the FETS can be configured with separately biased front and back gates. One gate can be biased separately from the other gate in a predetermined manner to enhance read stability of the asymmetrical cell.

摘要翻译： 提供了在不对称存储单元中采用独立门控制的技术。 诸如SRAM电路的存储器电路可以包括多个位线结构，与位线结构相交以形成多个单元位置的多个字线结构以及位于单元的多个非对称存储单元 位置。 每个非对称单元可以在相应的一个字线结构的控制下选择性地耦合到位线结构中的对应的一个。 每个单元可以包括多个场效应晶体管（FETS），并且FETS中的至少一个可以被配置为单独偏置的前门和后门。 一个栅极可以以预定的方式与另一个栅极分开偏置，以增强不对称单元的读取稳定性。

公开(公告)号：US20060227595A1

公开(公告)日：2006-10-12

申请号：US11100893

申请日：2005-04-07

申请人： Ching-Te Chuang ,  Jae-Joon Kim ,  Keunwoo Kim

发明人： Ching-Te Chuang ,  Jae-Joon Kim ,  Keunwoo Kim

IPC分类号： G11C11/00

CPC分类号： G11C11/412

摘要： Disclosed is an eight transistor static random access memory (SRAM) device, comprising first and second inverters, a first bit line, a first complement bit line, a pair of write access transistors, and a pair of read access transistors. Each of the first and second inverters includes a respective pair of transistors, and has a respective data node. Each of a first and a second of the access transistors has a source, a drain, a front gate, and a back gate. The first access transistor is coupled to the first bit line, and the second access transistor is coupled to the first complement bit line. The back gate of the first access transistor is coupled to the data node of the first inverter; and the back gate of the second access transistor is coupled to the data node of the second inverter. This increases the difference between the threshold voltages of the first and second access transistors.

摘要翻译： 公开了一种八晶体管静态随机存取存储器（SRAM）器件，包括第一和第二反相器，第一位线，第一补码位线，一对写入存取晶体管和一对读存取晶体管。 第一和第二反相器中的每一个包括相应的晶体管对，并具有相应的数据节点。 第一和第二存取晶体管中的每一个具有源极，漏极，前栅极和后栅极。 第一存取晶体管耦合到第一位线，第二存取晶体管耦合到第一补码位线。 第一存取晶体管的背栅极耦合到第一反相器的数据节点; 并且第二存取晶体管的背栅极耦合到第二反相器的数据节点。 这增加了第一和第二存取晶体管的阈值电压之间的差异。

公开(公告)号：US20120087196A1

公开(公告)日：2012-04-12

申请号：US13075682

申请日：2011-03-30

申请人： Hao-I YANG ,  Ching-Te Chuang ,  Wei Hwang

发明人： Hao-I YANG ,  Ching-Te Chuang ,  Wei Hwang

IPC分类号： G11C5/14

CPC分类号： G11C11/417

摘要： The present invention proposes a gate oxide breakdown-withstanding power switch structure, which is connected with an SRAM and comprises a first CMOS switch and a second CMOS switch respectively having different gate-oxide thicknesses or different threshold voltages. The CMOS switch, which has a normal gate-oxide thickness or a normal threshold voltage, provides current for the SRAM to wake up the SRAM from a standby or sleep mode to an active mode. The CMOS switch, which has a thicker gate-oxide thickness or a higher threshold voltage, provides current for the SRAM to work in an active mode. The present invention prevents a power switch from gate-oxide breakdown lest noise margin, stabilization and performance of SRAM be affected.

摘要翻译： 本发明提出一种栅极氧化物击穿电源开关结构，其与SRAM连接，并且包括分别具有不同栅极氧化物厚度或不同阈值电压的第一CMOS开关和第二CMOS开关。 具有正常栅极氧化物厚度或正常阈值电压的CMOS开关为SRAM提供电流，以将SRAM从待机或睡眠模式唤醒至活动模式。 具有更厚栅极氧化物厚度或更高阈值电压的CMOS开关为SRAM提供工作在主动模式的电流。 本发明防止电源开关从栅极氧化层击穿，以免噪声容限，SRAM的稳定性和性能受到影响。

公开(公告)号：US07973564B1

公开(公告)日：2011-07-05

申请号：US12874584

申请日：2010-09-02

申请人： Ching-Te Chuang ,  Chien-Yu Lu

发明人： Ching-Te Chuang ,  Chien-Yu Lu

IPC分类号： H03K19/094

CPC分类号： H03K17/04123

摘要： A high load driving device is disclosed. The driving device comprises an inverter receiving a digital voltage. The inverter reverses the digital voltage, and then sends out it. The output terminal of the inverter is coupled to a capacitor, a first P-type field-effect transistor (FET), a second P-type FET, a first N-type FET, and a third N-type FET. A push-up circuit is composed of these transistors and a second N-type FET and coupled to a P-type push-up FET. A load is coupled to a high voltage through the P-type push-up FET. When the digital voltage rises from a low level to a high level, the push-up circuit utilizes the original voltage drop of the capacitor to control the P-type push-up FET, whereby the gate voltage of the P-type push-up FET is at a low stabilization voltage that is lower than the ground potential. Then, the load is driven rapidly.

摘要翻译： 公开了一种高负载驱动装置。 驱动装置包括接收数字电压的逆变器。 逆变器反转数字电压，然后发出。 反相器的输出端子耦合到电容器，第一P型场效应晶体管（FET），第二P型FET，第一N型FET和第三N型FET。 上推电路由这些晶体管和第二N型FET组成并耦合到P型上推FET。 负载通过P型上推FET耦合到高电压。 当数字电压从低电平上升到高电平时，上推电路利用电容器的原始电压降来控制P型上推FET，由此P型上推电压的栅极电压 FET处于低于地电位的低稳定电压。 然后，负载被快速驱动。

公开(公告)号：US20110128796A1

公开(公告)日：2011-06-02

申请号：US12772238

申请日：2010-05-03

申请人： Ching-Te Chuang ,  Hao-I Yang ,  Jihi-Yu Lin ,  Shyh-Chyi Yang ,  Ming-Hsien Tu ,  Wei Hwang ,  Shyh-Jye Jou ,  Kun-Ti Lee ,  Hung-Yu Li

发明人： Ching-Te Chuang ,  Hao-I Yang ,  Jihi-Yu Lin ,  Shyh-Chyi Yang ,  Ming-Hsien Tu ,  Wei Hwang ,  Shyh-Jye Jou ,  Kun-Ti Lee ,  Hung-Yu Li

IPC分类号： G11C7/10 ,  G11C7/00

CPC分类号： G11C11/412

摘要： A disturb-free static random access memory cell includes: a latch circuit having a first access terminal and a second access terminal; a first switching circuit having a first bit transferring terminal coupled to the first access terminal, a first control terminal coupled to a first write word line, and a second bit transferring terminal; a second switching circuit having a third bit transferring terminal coupled to the second access terminal, a second control terminal coupled to a second write word line, and a fourth bit transferring terminal coupled to the second bit transferring terminal; a third switching circuit having a fifth bit transferring terminal coupled to the fourth bit transferring terminal, a third control terminal coupled to a word line, and a sixth bit transferring terminal coupled to a bit line; and a sensing amplifier coupled to the bit line, for determining a bit value appearing at the bit line.

摘要翻译： 无干扰的静态随机存取存储单元包括：具有第一接入终端和第二接入终端的锁存电路; 第一切换电路，具有耦合到第一接入终端的第一比特传送终端，耦合到第一写字线的第一控制终端和第二比特传送终端; 第二切换电路，具有耦合到第二接入终端的第三比特传送终端，耦合到第二写字线的第二控制终端，以及耦合到第二比特传送终端的第四比特传送终端。 第三开关电路，具有耦合到第四位转移终端的第五位转移终端，耦合到字线的第三控制端和耦合到位线的第六位转移端; 以及耦合到位线的感测放大器，用于确定出现在位线处的位值。

公开(公告)号：US07903450B2

公开(公告)日：2011-03-08

申请号：US12040966

申请日：2008-03-03

申请人： Ching-Te Chuang ,  Jae-Joon Kim ,  Keunwoo Kim

发明人： Ching-Te Chuang ,  Jae-Joon Kim ,  Keunwoo Kim

IPC分类号： G11C11/00

CPC分类号： G11C11/412 ,  H01L27/1104

摘要： Asymmetrical SRAM cells are improved by providing one or more of improved read stability and improved write performance and margin. A first inverter and a second inverter are cross-coupled and configured for selective coupling to true and complementary bit lines under control of read and write word lines. The first inverter is formed by a first, n-type, FET (NFET) and a second, p-type, FET (PFET). Process and/or technology approaches can be employed to adjust the relative strength of the FETS to obtain, for example, read margin, write margin, and/or write performance improvements.

摘要翻译： 通过提供改进的读取稳定性和改进的写入性能和余量的一个或多个来改进非对称SRAM单元。 第一反相器和第二反相器被交叉耦合并且被配置为在读和写字线的控制下选择性地耦合到真和互补的位线。 第一反相器由第一n型FET（NFET）和第二p型FET（PFET）形成。 可以采用过程和/或技术方法来调整FET的相对强度，以获得例如读取余量，写入裕度和/或写入性能改进。

公开(公告)号：US20090302894A1

公开(公告)日：2009-12-10

申请号：US11859351

申请日：2007-09-21

申请人： Ching-Te Chuang ,  Keunwoo Kim ,  Jente Benedict Kuang ,  Kevin John Nowka

发明人： Ching-Te Chuang ,  Keunwoo Kim ,  Jente Benedict Kuang ,  Kevin John Nowka

IPC分类号： H03K19/20 ,  H03K19/096

CPC分类号： H03K19/0963

摘要： A dynamic logic gate has a device for charging a dynamic node during a pre-charge phase of a clock. A logic tree evaluates the dynamic node with a device during an evaluate phase of the clock. The dynamic node has a keeper circuit comprising an inverter with its input coupled to the dynamic node and its output coupled to the back gate of a dual gate PFET device. The source of the dual gate PFET is coupled to the power supply and its drain is coupled to the dynamic node forming a half latch. The front gate of the dual gate PFET is coupled to a logic circuit with a mode input and a logic input coupled back to a node sensing the state of the dynamic node. The mode input may be a slow mode to preserve dynamic node state or the clock delayed that turns ON the strong keeper after evaluation.

摘要翻译： 动态逻辑门具有用于在时钟的预充电阶段对动态节点充电的装置。 逻辑树在时钟的评估阶段使用设备来评估动态节点。 动态节点具有保持器电路，其包括反相器，其输入耦合到动态节点，其输出耦合到双栅极PFET器件的背栅极。 双栅极PFET的源极耦合到电源，并且其漏极耦合到形成半锁存器的动态节点。 双栅极PFET的前栅极耦合到具有模式输入和逻辑输入的逻辑电路，逻辑输入耦合回到感测动态节点的状态的节点。 模式输入可能是缓慢的模式，以保持动态节点状态或时钟延迟，在评估后打开强守护者。