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    SINGLE-ENDED SRAM WITH CROSS-POINT DATA-AWARE WRITE OPERATION
    1.
    发明申请
    SINGLE-ENDED SRAM WITH CROSS-POINT DATA-AWARE WRITE OPERATION 有权
    具有跨点数据写入操作的单端SRAM

    公开(公告)号：US20130194861A1

    公开(公告)日：2013-08-01

    申请号：US13562330

    申请日：2012-07-31

    申请人： Shyh-Jye Jou ,  Jhih-Yu Lin ,  Ching-Te Chuang ,  Ming-Hsien Tu ,  Yi-Wei Chiu

    发明人： Shyh-Jye Jou ,  Jhih-Yu Lin ,  Ching-Te Chuang ,  Ming-Hsien Tu ,  Yi-Wei Chiu

    IPC分类号： G11C11/00

    CPC分类号： G11C11/412

    摘要： A single-ended SRAM including at least one memory cell and a third switch is provided. The memory cell includes a data-latching unit, a first switch, a second switch and a data-transferring unit. The data-latching unit is configured for latching the received input data and provides a storage data and the inverse data of the storage data. The first switch transfers a reference data to the data-latching unit according to a first word-line signal. The second switch transfers the reference data to the data-latching unit according to a second word-line signal. The data-transferring unit decides whether or not to transfer the reference data to the bit-line according to the storage data and a control signal. The third switch receives the reference data and the control signal and transfers the reference data to the first switch, the second switch and the data-transferring unit according to the control signal.

    摘要翻译： 提供包括至少一个存储单元和第三开关的单端SRAM。 存储单元包括数据锁存单元，第一开关，第二开关和数据传送单元。 数据锁存单元被配置为锁存接收到的输入数据，并提供存储数据和存储数据的逆数据。 第一开关根据第一字线信号将参考数据传送到数据锁存单元。 第二开关根据第二字线信号将参考数据传送到数据锁存单元。 数据传送单元根据存储数据和控制信号决定是否将参考数据传送到位线。 第三开关接收参考数据和控制信号，并根据控制信号将参考数据传送到第一开关，第二开关和数据传送单元。

    Reduced-width low-error multiplier
    3.
    发明授权
    Reduced-width low-error multiplier 失效
    缩减宽度低误差乘数

    公开(公告)号：US06957244B2

    公开(公告)日：2005-10-18

    申请号：US09861555

    申请日：2001-05-22

    申请人： Shyh-Jye Jou ,  Hui-Hsuan Wang

    发明人： Shyh-Jye Jou ,  Hui-Hsuan Wang

    IPC分类号： G06F7/52 ,  G06F7/533 ,  G06F7/38

    CPC分类号： G06F7/523 ,  G06F7/49942 ,  G06F7/5338

    摘要： This invention discloses a reduced-width, low-error multiplier that can be used in Digital Signal Processing (DSP). Specifically, this invention relates to a reduced-width, low-error multiplier capable of processing digital signals of communication systems such as a timing recovery circuit, a carrier recovery circuit, and a FIR filter, etc. This invention derives a binary compensation vector to compensate for the error caused by the reduction of area without any hardware overhead, and implements the compensation structure of an Array and a Booth multiplier to reduce hardware complexity.

    摘要翻译： 本发明公开了一种可用于数字信号处理（DSP）的缩小宽度低误差乘法器。 具体地，本发明涉及能够处理定时恢复电路，载波恢复电路和FIR滤波器等通信系统的数字信号的缩小宽度低误差乘法器。本发明导出二进制补偿矢量 补偿由于减少面积而导致的错误，无需任何硬件开销，并实现阵列和布乘乘法器的补偿结构，以降低硬件复杂性。

    Low noise output buffer
    4.
    发明授权
    Low noise output buffer 失效
    低噪声输出缓冲器

    公开(公告)号：US06265892B1

    公开(公告)日：2001-07-24

    申请号：US09371199

    申请日：1999-08-10

    申请人： Shyh-Jye Jou ,  Ray-De Chiao ,  Shu-Hua Kuo ,  Tin-Hao Lin

    发明人： Shyh-Jye Jou ,  Ray-De Chiao ,  Shu-Hua Kuo ,  Tin-Hao Lin

    IPC分类号： H03K1716

    CPC分类号： H03K17/167

    摘要： A low noise output buffer to simultaneously reduce switching noise and output signal ringing for output ringing and maintain DC current. A temporary and a steady-state output buffers are supplied by a buffer voltage source and an internal circuit voltage source, respectively. Each driver has a pull-up and a pull-down transistors. While switching the output buffer from a high voltage level to a low voltage level or from a low voltage level to a high voltage level, a predriver and a single steady-state circuit are designed to respectively generate a large simultaneous switching noise at the buffer voltage source and a small simultaneous switching noise at the internal circuit voltage source. A Schmitt trigger circuit is also used to turn off the temporary driver, so as to reduce the output signal ringing while the steady-state driver maintains a supply of DC current. In another design of a low noise output buffer to reduce ground bounces and output signal ringing as well as to maintain a DC current, a temporary driver is used. An adaptive characteristic of the low noise output buffer under different loading conditions is achieved by a feedback circuit. The temporary driver is turned on only during the middle period of output transition time to provide an additional charging or discharging current. Since the temporary driver is always off apart from the transition period, the effect of reducing ground bounces and output signal ringing can thus be outstanding.

    摘要翻译： 低噪声输出缓冲器，可同时降低开关噪声和输出信号振铃以进行输出振铃并保持直流电流。 分别由缓冲电压源和内部电路电压源提供临时和稳态输出缓冲器。 每个驱动器都有一个上拉和一个下拉晶体管。 当将输出缓冲器从高电压电平切换到低电压电平或从低电压电平切换到高电压电平时，预驱动器和单稳态电路被设计为分别在缓冲电压下产生大的同时开关噪声 源极和内部电路电压源的小的同时开关噪声。 施密特触发电路也用于关断临时驱动器，以便在稳态驱动器保持直流电流供应时减少输出信号振铃。 在另一种低噪声输出缓冲器的设计中，为了减少地面跳动和输出信号振铃以及维持直流电流，使用临时驱动器。 通过反馈电路实现了不同负载条件下低噪声输出缓冲器的自适应特性。 临时驱动器仅在输出转换时间的中间期间接通，以提供额外的充电或放电电流。 由于临时驾驶员始终偏离过渡期，所以减少地面反弹和输出信号振铃的效果因此可以突出。

    Threshold voltage measurement device
    5.
    发明授权
    Threshold voltage measurement device 有权
    阈值电压测量装置

    公开(公告)号：US08582378B1

    公开(公告)日：2013-11-12

    申请号：US13597733

    申请日：2012-08-29

    申请人： Ching-Te Chuang ,  Shyh-Jye Jou ,  Geng-Cing Lin ,  Shao-Cheng Wang ,  Yi-Wei Lin ,  Ming-Chien Tsai ,  Wei-Chiang Shih ,  Nan-Chun Lien ,  Kuen-Di Lee ,  Jyun-Kai Chu

    发明人： Ching-Te Chuang ,  Shyh-Jye Jou ,  Geng-Cing Lin ,  Shao-Cheng Wang ,  Yi-Wei Lin ,  Ming-Chien Tsai ,  Wei-Chiang Shih ,  Nan-Chun Lien ,  Kuen-Di Lee ,  Jyun-Kai Chu

    IPC分类号： G11C7/00 ,  G11C29/00

    CPC分类号： G11C29/50004 ,  G11C11/41 ,  G11C29/12005

    摘要： A threshold voltage measurement device is disclosed. The device is coupled to a 6T SRAM. The SRAM comprises two inverters each coupled to a FET. Power terminals of one inverter are in a floating state; the drain and source of the FET coupled to the inverter are short-circuited. Two voltage selectors, a resistor, an amplifier and the SRAM are connected in a negative feedback way. Different bias voltages are applied to the SRAM for measuring threshold voltages of two FETs of the other inverter and the FET coupled to the other inverter. The present invention uses a single circuit to measure the threshold voltages of the three FETs without changing the physical structure of the SRAM. Thereby is accelerated the measurement and decreased the cost of the fabrication process and measurement instruments.

    摘要翻译： 公开了一种阈值电压测量装置。 该器件耦合到6T SRAM。 SRAM包括两个各自耦合到FET的反相器。 一个逆变器的电源端子处于浮动状态; 耦合到逆变器的FET的漏极和源极短路。 两个电压选择器，电阻，放大器和SRAM以负反馈的方式连接。 不同的偏置电压被施加到SRAM，用于测量另一个反相器的两个FET和耦合到另一个反相器的FET的阈值电压。 本发明使用单个电路来测量三个FET的阈值电压，而不改变SRAM的物理结构。 从而加快了测量并降低了制造过程和测量仪器的成本。

    SRAM writing system and related apparatus
    6.
    发明授权
    SRAM writing system and related apparatus 有权
    SRAM写入系统及相关设备

    公开(公告)号：US08325512B2

    公开(公告)日：2012-12-04

    申请号：US13070977

    申请日：2011-03-24

    申请人： Ching-Te Chuang ,  Wei-Chiang Shih ,  Hung-Yu Lee ,  Jihi-Yu Lin ,  Ming-Hsien Tu ,  Shyh-Jye Jou ,  Kun-Di Lee

    发明人： Ching-Te Chuang ,  Wei-Chiang Shih ,  Hung-Yu Lee ,  Jihi-Yu Lin ,  Ming-Hsien Tu ,  Shyh-Jye Jou ,  Kun-Di Lee

    IPC分类号： G11C11/00

    CPC分类号： G11C11/413

    摘要： SRAM writing system and related apparatus are provided. The writing system of the invention has a dummy replica writing circuit, a negative pulse controller and at least a normal writing circuit; each normal writing circuit includes a write driver and a negative pulse supplier. While writing, the dummy replica writing circuit drives a dummy replica bit-line, such that the negative pulse controller generates a negative pulse control signal according to level of the dummy replica bit-line. In each writing circuit, when the write driver conducts to connect an associated bit-line to a bias end for driving a level transition, the negative pulse supplier switches the bias end from an operation voltage to a different negative pulse voltage according to the received negative pulse control signal.

    摘要翻译： 提供了SRAM写入系统和相关装置。 本发明的写入系统具有虚拟副本写入电路，负脉冲控制器和至少一个正常写入电路; 每个正常写入电路包括写入驱动器和负脉冲供应器。 在写入时，虚拟副本写入电路驱动虚拟副本位线，使得负脉冲控制器根据虚拟副本位线的电平产生负脉冲控制信号。 在每个写入电路中，当写入驱动器将相关联的位线连接到用于驱动电平转换的偏置端时，负脉冲供应器根据接收到的负值将偏置端从工作电压切换到不同的负脉冲电压 脉冲控制信号。

    SRAM WRITING SYSTEM AND RELATED APPARATUS
    8.
    发明申请
    SRAM WRITING SYSTEM AND RELATED APPARATUS 有权
    SRAM写入系统及相关设备

    公开(公告)号：US20110235444A1

    公开(公告)日：2011-09-29

    申请号：US13070977

    申请日：2011-03-24

    申请人： Ching-Te Chuang ,  Wei-Chiang Shih ,  Hung-Yu Lee ,  Jihi-Yu Lin ,  Ming-Hsien Tu ,  Shyh-Jye Jou ,  Kun-Di Lee

    发明人： Ching-Te Chuang ,  Wei-Chiang Shih ,  Hung-Yu Lee ,  Jihi-Yu Lin ,  Ming-Hsien Tu ,  Shyh-Jye Jou ,  Kun-Di Lee

    IPC分类号： G11C7/00

    CPC分类号： G11C11/413

    摘要： SRAM writing system and related apparatus are provided. The writing system of the invention has a dummy replica writing circuit, a negative pulse controller and at least a normal writing circuit; each normal writing circuit includes a write driver and a negative pulse supplier. While writing, the dummy replica writing circuit drives a dummy replica bit-line, such that the negative pulse controller generates a negative pulse control signal according to level of the dummy replica bit-line. In each writing circuit, when the write driver conducts to connect an associated bit-line to a bias end for driving a level transition, the negative pulse supplier switches the bias end from an operation voltage to a different negative pulse voltage according to the received negative pulse control signal.

    摘要翻译： 提供SRAM写入系统及相关装置。 本发明的写入系统具有虚拟副本写入电路，负脉冲控制器和至少一个正常写入电路; 每个正常写入电路包括写入驱动器和负脉冲供应器。 在写入时，虚拟副本写入电路驱动虚拟副本位线，使得负脉冲控制器根据虚拟副本位线的电平产生负脉冲控制信号。 在每个写入电路中，当写入驱动器将相关联的位线连接到用于驱动电平转换的偏置端时，负脉冲供应器根据接收到的负值将偏置端从工作电压切换到不同的负脉冲电压 脉冲控制信号。

    DISTURB-FREE STATIC RANDOM ACCESS MEMORY CELL
    10.
    发明申请
    DISTURB-FREE STATIC RANDOM ACCESS MEMORY CELL 有权
    无干扰的静态随机存取存储器单元

    公开(公告)号：US20110128796A1

    公开(公告)日：2011-06-02

    申请号：US12772238

    申请日：2010-05-03

    申请人： Ching-Te Chuang ,  Hao-I Yang ,  Jihi-Yu Lin ,  Shyh-Chyi Yang ,  Ming-Hsien Tu ,  Wei Hwang ,  Shyh-Jye Jou ,  Kun-Ti Lee ,  Hung-Yu Li

    发明人： Ching-Te Chuang ,  Hao-I Yang ,  Jihi-Yu Lin ,  Shyh-Chyi Yang ,  Ming-Hsien Tu ,  Wei Hwang ,  Shyh-Jye Jou ,  Kun-Ti Lee ,  Hung-Yu Li

    IPC分类号： G11C7/10 ,  G11C7/00

    CPC分类号： G11C11/412

    摘要： A disturb-free static random access memory cell includes: a latch circuit having a first access terminal and a second access terminal; a first switching circuit having a first bit transferring terminal coupled to the first access terminal, a first control terminal coupled to a first write word line, and a second bit transferring terminal; a second switching circuit having a third bit transferring terminal coupled to the second access terminal, a second control terminal coupled to a second write word line, and a fourth bit transferring terminal coupled to the second bit transferring terminal; a third switching circuit having a fifth bit transferring terminal coupled to the fourth bit transferring terminal, a third control terminal coupled to a word line, and a sixth bit transferring terminal coupled to a bit line; and a sensing amplifier coupled to the bit line, for determining a bit value appearing at the bit line.

    摘要翻译： 无干扰的静态随机存取存储单元包括：具有第一接入终端和第二接入终端的锁存电路; 第一切换电路，具有耦合到第一接入终端的第一比特传送终端，耦合到第一写字线的第一控制终端和第二比特传送终端; 第二切换电路，具有耦合到第二接入终端的第三比特传送终端，耦合到第二写字线的第二控制终端，以及耦合到第二比特传送终端的第四比特传送终端。 第三开关电路，具有耦合到第四位转移终端的第五位转移终端，耦合到字线的第三控制端和耦合到位线的第六位转移端; 以及耦合到位线的感测放大器，用于确定出现在位线处的位值。