FREEZE LOGIC
    21.
    发明申请
    FREEZE LOGIC 审中-公开

    公开(公告)号:US20180356464A1

    公开(公告)日:2018-12-13

    申请号:US15780009

    申请日:2016-12-01

    Abstract: A first plurality of logic gates and a second plurality of logic gates may be associated with a symmetric configuration. A first output at a first value may be generated by the first plurality of logic gates based on a first portion of input signals. A second output may be generated by the second plurality of logic gates at the first value based on a second portion of the input signals. A subsequent first output at a particular value may be generated by the first plurality of logic gates based on a first portion of a second plurality of input signals and a subsequent second output maybe generated by the second plurality of logic gates based on a second portion of the second plurality of input signals. A value of the subsequent second output may be complementary to the particular value of the subsequent first output.

    Constant time secure arithmetic-to-Boolean mask conversion

    公开(公告)号:US11822704B2

    公开(公告)日:2023-11-21

    申请号:US17290027

    申请日:2019-10-28

    CPC classification number: G06F21/72 G06F21/755 H04L9/003

    Abstract: A first arithmetic input share and a second arithmetic input share of an initial arithmetically-masked cryptographic value are received. A sequence of operations using the arithmetic input shares and a randomly generated number is performed, where a current operation in the sequence of operations generates a corresponding intermediate value that is used in a subsequent operation. At the end of the sequence of operations, a first Boolean output share and a second Boolean output share are generated. The arithmetic-to-Boolean mask conversion is independent of the input bit length.

    Memory optimization for nested hash operations

    公开(公告)号:US11539509B2

    公开(公告)日:2022-12-27

    申请号:US17248495

    申请日:2021-01-27

    Abstract: Disclosed is a method and a system to execute the method to perform a first hashing operation to compute a first hash value, store the first hash value in a plurality of output registers, store a second message in a plurality of input registers, perform a first iteration of a second hashing operation, with an input to the second hashing operation including the second message and the first hash value, determine that a first portion of the second message, stored in a first register of the plurality of input registers, has been processed in course of the second hashing operation, and move a first portion of the first hash value stored in a first register of the plurality of output registers to the first register of the plurality of input registers.

    FUNCTIONS WITH A PRE-CHARGE OPERATION AND AN EVALUATION OPERATION

    公开(公告)号:US20220191004A1

    公开(公告)日:2022-06-16

    申请号:US17598189

    申请日:2020-04-01

    Abstract: An input data may be received. A portion of a cryptographic operation may be performed with the received input data at a first function component. During the performance of the cryptographic operation at the first function component, a pre-charge operation may be performed at a second function component. Furthermore, the second function component may be used to perform another portion of the cryptographic operation with a result of the portion of the cryptographic operation performed at the first function component.

    EFFICIENT SIDE-CHANNEL-ATTACK-RESISTANT MEMORY ENCRYPTOR BASED ON KEY UPDATE

    公开(公告)号:US20220182232A1

    公开(公告)日:2022-06-09

    申请号:US17601205

    申请日:2020-04-04

    Abstract: Disclosed are memory encryption systems and methods that rotate encryption keys for robust resistance against side-channel-analysis (SCA)-based attacks on communication paths between an encryption engine within a trust boundary and an external memory component. A key data structure has a plurality of keys that are used to encrypt a plurality of memory blocks in the external memory. The memory blocks encrypted with the oldest key of the key data structure are identified. Encrypted data is read from the identified memory blocks. The encrypted data is decrypted from the identified memory blocks. The data is then re-encrypted using the selected key that is newer than the oldest key, and re-written to the identified memory blocks.

    Memory optimization for nested hash operations

    公开(公告)号:US10911221B2

    公开(公告)日:2021-02-02

    申请号:US16656286

    申请日:2019-10-17

    Abstract: A first hash value is calculated by using a first input value that is stored in a first set of registers. The first hash value is then stored in a second set of registers. A second input value is stored in the first set of registers after calculating the first hash value. The second hash value is calculated based on the first hash value and the second input value. During the calculating of the second hash value, the first hash value is shifted from the second set of registers to a portion of the first set of registers when the calculating of the second hash value has reached a state where the portion of the first set of registers is no longer used to store the second input value.

    MEMORY OPTIMIZATION FOR NESTED HASH OPERATIONS

    公开(公告)号:US20170359168A1

    公开(公告)日:2017-12-14

    申请号:US15603342

    申请日:2017-05-23

    Abstract: A first hash value is calculated by using a first input value that is stored in a first set of registers. The first hash value is then stored in a second set of registers. A second input value is stored in the first set of registers after calculating the first hash value. The second hash value is calculated based on the first hash value and the second input value. During the calculating of the second hash value, the first hash value is shifted from the second set of registers to a portion of the first set of registers when the calculating of the second hash value has reached a state where the portion of the first set of registers is no longer used to store the second input value.

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