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公开(公告)号：US11983280B2
公开(公告)日：2024-05-14
申请号：US17309937
申请日：2020-01-06
CPC分类号： G06F21/602 , G06F7/523 , G06F7/588 , G06F17/16 , G06F21/78
摘要： Aspects of the present disclosure involve a method and a system to support execution of the method to perform a cryptographic operation involving a first vector and a second vector, by projectively scaling the first vector, performing a first operation involving the scaled first vector and the second vector to obtain a third vector, generating a random number, storing the third vector in a first location, responsive to the random number having a first value, or in a second location, responsive to the random number having a second value, and performing a second operation involving a first input and a second input, wherein, based on the random number having the first value or the second value, the first input is the third vector stored in the first location or the second location and the second input is a fourth vector stored in the second location or the first location.
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2.发明申请公开(公告)号：US20210173618A1
公开(公告)日：2021-06-10
申请号：US17124374
申请日：2020-12-16
发明人： Michael Hutter , Michael Tunstall
IPC分类号： G06F7/76 , G06F7/58 , G09C1/00 , H04L9/14 , G06F21/72 , H04L9/30 , G06F7/00 , H04L9/00 , H04L9/06
摘要： A first input share value, a second input share value, and a third input share value may be received. The first input share value may be converted to a summation or subtraction between an input value and a combination of the second input share value and the third input share value. A random number value may be generated and combined with the second input share value and the third input share value to generate a combined value. Furthermore, a first output share value may be generated based on a combination of the converted first input share value, the combined value, and additional random number values.
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公开(公告)号：US20200067695A1
公开(公告)日：2020-02-27
申请号：US16666017
申请日：2019-10-28
摘要： An integrated circuit may implement a masked substitution box that includes substitution function components, a decoder, and a logic component. Each of the substitution function components may receive a same input value and a different mask value and may generate a respective output mask value based on the same input value and respective different mask value The decoder may receive an input mask value and generate a decoded output value that is based on the received input mask value. The logic component may select one of the output mask values from one of the substitution function components based on the decoded output value.
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公开(公告)号：US11914870B2
公开(公告)日：2024-02-27
申请号：US17435360
申请日：2020-03-04
IPC分类号： G06F3/06
CPC分类号： G06F3/0623 , G06F3/0655 , G06F3/0679
摘要： Aspects of the present disclosure calculate masked data shares dynamically inside the CPU boundary, and use a plurality of memory channels to write the masked data shares to an external memory location and/or to read the data shares from that external memory location. Each dynamically generated mask value is uniquely associated with a corresponding memory channel during writing data to the external memory. The modified masked data is unmasked or remasked during a subsequent read operation.
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公开(公告)号：US11863670B2
公开(公告)日：2024-01-02
申请号：US17601205
申请日：2020-04-04
发明人： Mark Evan Marson , Michael Hutter , Bart Stevens
CPC分类号： H04L9/0891 , H04L9/003 , H04L9/16
摘要： Disclosed are memory encryption systems and methods that rotate encryption keys for robust resistance against side-channel-analysis (SCA)-based attacks on communication paths between an encryption engine within a trust boundary and an external memory component. A key data structure has a plurality of keys that are used to encrypt a plurality of memory blocks in the external memory. The memory blocks encrypted with the oldest key of the key data structure are identified. Encrypted data is read from the identified memory blocks. The encrypted data is decrypted from the identified memory blocks. The data is then re-encrypted using the selected key that is newer than the oldest key, and re-written to the identified memory blocks.
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公开(公告)号：US20210226775A1
公开(公告)日：2021-07-22
申请号：US17248495
申请日：2021-01-27
发明人： Michael Hutter , Matthew Pond Baker
摘要： Disclosed is a method and a system to execute the method to perform a first hashing operation to compute a first hash value, store the first hash value in a plurality of output registers, store a second message in a plurality of input registers, perform a first iteration of a second hashing operation, with an input to the second hashing operation including the second message and the first hash value, determine that a first portion of the second message, stored in a first register of the plurality of input registers, has been processed in course of the second hashing operation, and move a first portion of the first hash value stored in a first register of the plurality of output registers to the first register of the plurality of input registers.
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公开(公告)号：US10712385B2
公开(公告)日：2020-07-14
申请号：US15780009
申请日：2016-12-01
发明人： Michael Hutter , Matthew Pond Baker
IPC分类号： G01R31/317 , G06F21/75 , H04L9/00 , G09C1/00 , G06F21/72 , G01R31/3177 , G06F21/55
摘要： A first plurality of logic gates and a second plurality of logic gates may be associated with a symmetric configuration. A first output at a first value may be generated by the first plurality of logic gates based on a first portion of input signals. A second output may be generated by the second plurality of logic gates at the first value based on a second portion of the input signals. A subsequent first output at a particular value may be generated by the first plurality of logic gates based on a first portion of a second plurality of input signals and a subsequent second output maybe generated by the second plurality of logic gates based on a second portion of the second plurality of input signals. A value of the subsequent second output may be complementary to the particular value of the subsequent first output.
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公开(公告)号：US10461925B2
公开(公告)日：2019-10-29
申请号：US15673284
申请日：2017-08-09
摘要： An integrated circuit may implement a masked substitution box that includes a counter that generates counter values. An input mask component may generate unmasked input values based on a combination of respective counter values and an input mask value. Furthermore, a substitution function component may receive the unmasked input values and may generate output values based on respective unmasked input values and a substitution function. An output mask component may generate masked output values based on a combination of respective output values and an output mask value. The masked output values may be stored at memory elements.
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公开(公告)号：US20180212761A1
公开(公告)日：2018-07-26
申请号：US15856682
申请日：2017-12-28
发明人： Begül Bilgin , Michael Hutter
CPC分类号： H04L9/0631 , H04L9/0625 , H04L9/065 , H04L9/0861
摘要： Systems and methods for efficient computation of stream ciphers. An example system for implementing a stream cipher, may comprise: a sub-round computation circuit of a first type configured to perform a subset of transformations of a cipher computation round on a round input state, each transformation of the subset of transformations including at least one of: a bitwise addition operation, a bitwise exclusive disjunction operation, or a bitwise rotation operation. The sub-round computation circuit of the first type may comprise: one or more of sub-round computation circuits of a second type, wherein each sub-round computation circuit of the second type is configured to perform the subset of transformations of the cipher computation round on a respective part of the round input state.
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公开(公告)号：US11353504B2
公开(公告)日：2022-06-07
申请号：US16913479
申请日：2020-06-26
发明人： Michael Hutter , Matthew Pond Baker
IPC分类号： G01R31/317 , G06F21/75 , H04L9/00 , G09C1/00 , G06F21/72 , G01R31/3177 , G06F21/55
摘要： A first plurality of logic gates and a second plurality of logic gates may be associated with a symmetric configuration. A first output at a first value may be generated by the first plurality of logic gates based on a first portion of input signals. A second output may be generated by the second plurality of logic gates at the first value based on a second portion of the input signals. A subsequent first output at a particular value may be generated by the first plurality of logic gates based on a first portion of a second plurality of input signals and a subsequent second output may be generated by the second plurality of logic gates based on a second portion of the second plurality of input signals. A value of the subsequent second output may be complementary to the particular value of the subsequent first output.
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