公开(公告)号：US6011788A

公开(公告)日：2000-01-04

申请号：US987815

申请日：1997-12-10

申请人： Michael Hurst ,  Johnny Harris ,  Dan M. Griffin ,  Lee Butterfield ,  Thomas R. Giallorenzi ,  Kyle L. Henderson

发明人： Michael Hurst ,  Johnny Harris ,  Dan M. Griffin ,  Lee Butterfield ,  Thomas R. Giallorenzi ,  Kyle L. Henderson

IPC分类号： H04B7/26 ,  H04L7/08 ,  H04W56/00 ,  H04B7/216

CPC分类号： H04W56/0015

摘要： A method is disclosed for operating a synchronous Code Division Multiple Access (S-CDMA) radio frequency communication system having a host transceiver unit and a plurality of user transceiver units. The method includes an initial step of defining a super-frame to be comprised of N sequential frames of data. In the preferred embodiment N is equal to three. For a user transceiver unit that obtains access to the host transceiver unit a next step of the method receives frames of data transmitted by the host transceiver unit and initially aligns a receiver timing and a transmitter timing of the user transceiver unit to a super-frame boundary of the received frames. A next step transmits frames of data from the user transceiver unit to the host transceiver unit using the initial timing alignment. A further step of the method detects at the host transceiver unit a difference between the arrival of the transmitted frames of data and a super-frame boundary and then transmits a timing correction parameter, preferably expressed in symbols, from the host transceiver unit to the user transceiver unit in order to align the transmitted frames of data to the super-frame boundary.

摘要翻译： 公开了一种用于操作具有主机收发器单元和多个用户收发器单元的同步码分多址（S-CDMA）射频通信系统的方法。 该方法包括定义由N个连续数据帧组成的超帧的初始步骤。 在优选实施例中，N等于3。 对于获得对主收发器单元的访问的用户收发器单元，该方法的下一步骤接收主机收发器单元发送的数据帧，并且最初将用户收发器单元的接收机定时和发送器定时对齐到超帧边界 的接收帧。 下一步骤将使用初始定时对准将数据帧从用户收发器单元发送到主机收发器单元。 该方法的另一步骤在主机收发器单元处检测所发送的数据帧的到达与超帧边界之间的差异，然后将来自主收发器单元的优选地以符号表示的定时校正参数发送到用户 收发器单元，以便将发送的数据帧对齐到超帧边界。

公开(公告)号：US4121290A

公开(公告)日：1978-10-17

申请号：US788371

申请日：1977-04-18

申请人： Royce Allen ,  Jerry L. Sutton ,  Dan M. Griffin ,  Hal W. Frye ,  Joseph G. Colborn

发明人： Royce Allen ,  Jerry L. Sutton ,  Dan M. Griffin ,  Hal W. Frye ,  Joseph G. Colborn

IPC分类号： G01H5/00 ,  G06G7/48 ,  G06G7/78 ,  H04B13/00

CPC分类号： G01H5/00 ,  G06G7/48

摘要： An analog apparatus for determining the velocity of sound at a selected position in a liquid media is provided with a means for representing the conductivity, temperature, and depth of the position in the form of analog voltages, and is further provided with an analog calculating means receiving each of the voltages for calculating the velocity of sound as a function of conductivity, temperature, and depth. The sound velocity may be calculated at a succession of positions to provide a sound velocity versus depth profile of the liquid media.

摘要翻译： 用于确定液体介质中选定位置处的声速的模拟装置具有用于以模拟电压的形式表示位置的电导率，温度和深度的装置，还具有模拟计算装置 接收用于计算作为电导率，温度和深度的函数的声速的每个电压。 可以在连续的位置处计算声速，以提供液体介质的声速与深度分布。

公开(公告)号：US4118782A

公开(公告)日：1978-10-03

申请号：US780750

申请日：1977-03-24

申请人： Royce H. Allen ,  Jerry L. Sutton ,  Dan M. Griffin ,  Hal W. Frye ,  Joseph G. Colborn

发明人： Royce H. Allen ,  Jerry L. Sutton ,  Dan M. Griffin ,  Hal W. Frye ,  Joseph G. Colborn

IPC分类号： G01H5/00 ,  G01P3/00

CPC分类号： G01H5/00

摘要： A digital apparatus for determining the velocity of sound at a selected position in a liquid media is provided with a means for representing the conductivity, temperature and depth of the position in the form of digital numbers, and provides a digital calculating means receiving each of the digital numbers for calculating the velocity of sound as a function of conductivity, temperature, and depth. The sound velocity may be calculated at a succession of positions to provide sound velocity versus depth profile of the liquid media.

摘要翻译： 用于确定在液体介质中的选定位置处的声速的数字装置设置有用于以数字数字的形式表示位置的电导率，温度和深度的装置，并且提供数字计算装置， 用于计算声速作为电导率，温度和深度的函数的数字数字。 可以在连续的位置处计算声速，以提供液体介质的声速与深度曲线。

公开(公告)号：US07164733B1

公开(公告)日：2007-01-16

申请号：US10273929

申请日：2002-10-17

申请人： Dan M. Griffin ,  Randal R. Sylvester

发明人： Dan M. Griffin ,  Randal R. Sylvester

IPC分类号： H04L27/00

CPC分类号： H04L27/227 ,  H04L2027/003 ,  H04L2027/0055 ,  H04L2027/0067

摘要： A method and system for compensating digital data demodulation phase uncertainty is provided. The method includes the steps of identifying a phase reference quadrant, the phase reference quadrant having a phase reference axis and four quadrants, I, II, III, and IV; receiving known digital data; and forming a phase vector from the known digital data, determining which quadrant the phase vector is located in and rotating the phase vector to the phase reference quadrant if it is determined that the phase vector is not located in the phase reference quadrant. The last step generates a phase error signal proportional to the resulting angle by rotating the phase vector −45° and measuring the resulting angle between the phase vector and the phase reference axis.

摘要翻译： 提供了一种用于补偿数字数据解调相位不确定性的方法和系统。 该方法包括以下步骤：识别相位参考象限，相位参考象限具有相位参考轴和四个象限I，II，III和IV; 接收已知的数字数据; 以及如果确定相位矢量不位于相位参考象限中，则从已知的数字数据形成相位矢量，确定相位矢量所在的象限，并将相位矢量旋转到相位参考象限。 最后一步通过旋转相位矢量-45°并测量相位矢量和相位参考轴之间产生的角度，产生与所得到的角度成比例的相位误差信号。

公开(公告)号：US06285261B1

公开(公告)日：2001-09-04

申请号：US09610177

申请日：2000-07-05

申请人： George E. Pax ,  James E. O'Toole ,  Dan M. Griffin

发明人： George E. Pax ,  James E. O'Toole ,  Dan M. Griffin

IPC分类号： H03L100

CPC分类号： H03L7/0895 ,  H03L7/0896 ,  H03L7/113 ,  H04B1/707 ,  H04L7/033

摘要： A method of using a phase lock loop to receive an oscillating input signal and produce an output signal, the phase lock loop comprising a plurality of flip-flops which are chained together, the plurality of flip-flops including a first flip-flop having a first output, including a second flip-flop having an input coupled to the first output and having a second output, and including a third flip-flop having an input coupled to the second output, the phase lock loop further comprising a control node, the method including using the flip-flops to determine time spacing between transitions to perform a frequency comparison of the output signal relative to the input signal; extracting a clock from an input digital signal; and performing phase control and adjusting the voltage on the control node of the voltage controlled oscillator.

摘要翻译： 一种使用锁相环接收振荡输入信号并产生输出信号的方法，所述锁相环包括链接在一起的多个触发器，所述多个触发器包括具有第一触发器的第一触发器， 第一输出，包括具有耦合到第一输出并具有第二输出的输入的第二触发器，并且包括具有耦合到第二输出的输入的第三触发器，所述锁相环还包括控制节点， 方法，包括使用触发器来确定转变之间的时间间隔以执行输出信号相对于输入信号的频率比较; 从输入数字信号中提取时钟; 并执行相位控制和调节压控振荡器的控制节点上的电压。

公开(公告)号：US5774022A

公开(公告)日：1998-06-30

申请号：US707220

申请日：1996-08-29

申请人： Dan M. Griffin ,  George E. Pax ,  James E. O'Toole

发明人： Dan M. Griffin ,  George E. Pax ,  James E. O'Toole

IPC分类号： H03L7/089 ,  H03L7/113 ,  H04B1/707 ,  H04L7/033 ,  H03L7/10

CPC分类号： H03L7/113 ,  H03L7/0895 ,  H03L7/0896 ,  H04L7/033 ,  H04B1/707

摘要： A communications system including a clock recovery circuit that extracts a clock signal from incoming digital data, the clock recovery circuit including a voltage controlled oscillator having a control node and having an output producing an output wave having a frequency that varies in response to a voltage applied to the control node; charge pump and loop filter circuitry that controls the rate of change of the voltage on the control node of the voltage controlled oscillator; a start-up circuit that performs frequency detection and, in conjunction with the charge pump and loop filter circuitry, adjusts the voltage on the control node of the voltage controlled oscillator; and a state machine that performs phase detection and adjusts the voltage on the control node of the voltage controlled oscillator.

摘要翻译： 一种通信系统，包括从输入数字数据中提取时钟信号的时钟恢复电路，所述时钟恢复电路包括具有控制节点的压控振荡器，并具有产生具有响应于施加的电压而变化的频率的输出波的输出 到控制节点; 电荷泵和环路滤波器电路，用于控制压控振荡器的控制节点上的电压变化率; 启动电路，执行频率检测，并结合电荷泵和环路滤波器电路调节压控振荡器的控制节点上的电压; 以及执行相位检测并调节压控振荡器的控制节点上的电压的状态机。

公开(公告)号：US5982237A

公开(公告)日：1999-11-09

申请号：US5090

申请日：1998-01-09

申请人： George E. Pax ,  James E. O'Toole ,  Dan M. Griffin

发明人： George E. Pax ,  James E. O'Toole ,  Dan M. Griffin

IPC分类号： H03L7/089 ,  H03L7/113 ,  H04B1/707 ,  H04L7/033 ,  H03L1/00 ,  H03L7/18

CPC分类号： H03L7/113 ,  H03L7/0895 ,  H03L7/0896 ,  H04L7/033 ,  H04B1/707

摘要： A communications system including a clock recovery circuit that extracts a clock signal from incoming digital data, the clock recovery circuit comprising:a voltage controlled oscillator having a control node and having an output producing an output wave having a frequency that varies in response to a voltage applied to the control node; charge pump and loop filter circuitry that controls the rate of change of the voltage on the control node of the voltage controlled oscillator; a start-up circuit that performs frequency detection and, in conjunction with the charge pump and loop filter circuitry, adjusts the voltage on the control node of the voltage controlled oscillator; and a state machine that performs phase detection and adjusts the voltage on the control node of the voltage controlled oscillator.

摘要翻译： 一种通信系统，包括从输入的数字数据中提取时钟信号的时钟恢复电路，所述时钟恢复电路包括：具有控制节点并具有产生具有响应于电压而变化的频率的输出波的输出的压控振荡器 应用于控制节点; 电荷泵和环路滤波器电路，用于控制压控振荡器的控制节点上的电压变化率; 启动电路，执行频率检测，并结合电荷泵和环路滤波器电路调节压控振荡器的控制节点上的电压; 以及执行相位检测并调节压控振荡器的控制节点上的电压的状态机。

公开(公告)号：US4653074A

公开(公告)日：1987-03-24

申请号：US694656

申请日：1985-01-24

申请人： Dan M. Griffin ,  Clifford T. Johnson ,  Larry J. Miller

发明人： Dan M. Griffin ,  Clifford T. Johnson ,  Larry J. Miller

IPC分类号： H04L7/033 ,  H04L7/00 ,  H03K5/135

CPC分类号： H04L7/0331

摘要： A system for synchronizing information bits to any frequency signal chain with low jitter correction and adapted for gate array implementation.

摘要翻译： 一种用于将信息位同步到具有低抖动校正并适用于门阵列实现的任何频率信号链的系统。