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    Digital clock recovery loop
    1.
    发明授权
    Digital clock recovery loop 有权
    数字时钟恢复回路

    公开(公告)号：US06285261B1

    公开(公告)日：2001-09-04

    申请号：US09610177

    申请日：2000-07-05

    申请人： George E. Pax ,  James E. O'Toole ,  Dan M. Griffin

    发明人： George E. Pax ,  James E. O'Toole ,  Dan M. Griffin

    IPC分类号： H03L100

    CPC分类号： H03L7/0895 ,  H03L7/0896 ,  H03L7/113 ,  H04B1/707 ,  H04L7/033

    摘要： A method of using a phase lock loop to receive an oscillating input signal and produce an output signal, the phase lock loop comprising a plurality of flip-flops which are chained together, the plurality of flip-flops including a first flip-flop having a first output, including a second flip-flop having an input coupled to the first output and having a second output, and including a third flip-flop having an input coupled to the second output, the phase lock loop further comprising a control node, the method including using the flip-flops to determine time spacing between transitions to perform a frequency comparison of the output signal relative to the input signal; extracting a clock from an input digital signal; and performing phase control and adjusting the voltage on the control node of the voltage controlled oscillator.

    摘要翻译： 一种使用锁相环接收振荡输入信号并产生输出信号的方法，所述锁相环包括链接在一起的多个触发器，所述多个触发器包括具有第一触发器的第一触发器， 第一输出，包括具有耦合到第一输出并具有第二输出的输入的第二触发器，并且包括具有耦合到第二输出的输入的第三触发器，所述锁相环还包括控制节点， 方法，包括使用触发器来确定转变之间的时间间隔以执行输出信号相对于输入信号的频率比较; 从输入数字信号中提取时钟; 并执行相位控制和调节压控振荡器的控制节点上的电压。

    Digital clock recovery loop
    2.
    发明授权
    Digital clock recovery loop 失效
    数字时钟恢复回路

    公开(公告)号：US5774022A

    公开(公告)日：1998-06-30

    申请号：US707220

    申请日：1996-08-29

    申请人： Dan M. Griffin ,  George E. Pax ,  James E. O'Toole

    发明人： Dan M. Griffin ,  George E. Pax ,  James E. O'Toole

    IPC分类号： H03L7/089 ,  H03L7/113 ,  H04B1/707 ,  H04L7/033 ,  H03L7/10

    CPC分类号： H03L7/113 ,  H03L7/0895 ,  H03L7/0896 ,  H04L7/033 ,  H04B1/707

    摘要： A communications system including a clock recovery circuit that extracts a clock signal from incoming digital data, the clock recovery circuit including a voltage controlled oscillator having a control node and having an output producing an output wave having a frequency that varies in response to a voltage applied to the control node; charge pump and loop filter circuitry that controls the rate of change of the voltage on the control node of the voltage controlled oscillator; a start-up circuit that performs frequency detection and, in conjunction with the charge pump and loop filter circuitry, adjusts the voltage on the control node of the voltage controlled oscillator; and a state machine that performs phase detection and adjusts the voltage on the control node of the voltage controlled oscillator.

    摘要翻译： 一种通信系统，包括从输入数字数据中提取时钟信号的时钟恢复电路，所述时钟恢复电路包括具有控制节点的压控振荡器，并具有产生具有响应于施加的电压而变化的频率的输出波的输出 到控制节点; 电荷泵和环路滤波器电路，用于控制压控振荡器的控制节点上的电压变化率; 启动电路，执行频率检测，并结合电荷泵和环路滤波器电路调节压控振荡器的控制节点上的电压; 以及执行相位检测并调节压控振荡器的控制节点上的电压的状态机。

    Digital clock recovery loop
    3.
    发明授权
    Digital clock recovery loop 失效
    数字时钟恢复回路

    公开(公告)号：US5982237A

    公开(公告)日：1999-11-09

    申请号：US5090

    申请日：1998-01-09

    申请人： George E. Pax ,  James E. O'Toole ,  Dan M. Griffin

    发明人： George E. Pax ,  James E. O'Toole ,  Dan M. Griffin

    IPC分类号： H03L7/089 ,  H03L7/113 ,  H04B1/707 ,  H04L7/033 ,  H03L1/00 ,  H03L7/18

    CPC分类号： H03L7/113 ,  H03L7/0895 ,  H03L7/0896 ,  H04L7/033 ,  H04B1/707

    摘要： A communications system including a clock recovery circuit that extracts a clock signal from incoming digital data, the clock recovery circuit comprising:a voltage controlled oscillator having a control node and having an output producing an output wave having a frequency that varies in response to a voltage applied to the control node; charge pump and loop filter circuitry that controls the rate of change of the voltage on the control node of the voltage controlled oscillator; a start-up circuit that performs frequency detection and, in conjunction with the charge pump and loop filter circuitry, adjusts the voltage on the control node of the voltage controlled oscillator; and a state machine that performs phase detection and adjusts the voltage on the control node of the voltage controlled oscillator.

    摘要翻译： 一种通信系统，包括从输入的数字数据中提取时钟信号的时钟恢复电路，所述时钟恢复电路包括：具有控制节点并具有产生具有响应于电压而变化的频率的输出波的输出的压控振荡器 应用于控制节点; 电荷泵和环路滤波器电路，用于控制压控振荡器的控制节点上的电压变化率; 启动电路，执行频率检测，并结合电荷泵和环路滤波器电路调节压控振荡器的控制节点上的电压; 以及执行相位检测并调节压控振荡器的控制节点上的电压的状态机。

    Correlation apparatus and method for accommodating spreading code frequency offset
    5.
    发明授权
    Correlation apparatus and method for accommodating spreading code frequency offset 有权
    适应扩展码频偏的相关装置和方法

    公开(公告)号：US08073084B1

    公开(公告)日：2011-12-06

    申请号：US12691578

    申请日：2010-01-21

    申请人： Thomas R. Giallorenzi ,  Johnny M. Harris ,  Dan M. Griffin ,  Richard Ertel ,  Eric K. Hall

    发明人： Thomas R. Giallorenzi ,  Johnny M. Harris ,  Dan M. Griffin ,  Richard Ertel ,  Eric K. Hall

    IPC分类号： H03D1/00

    CPC分类号： H04B1/7093 ,  H04B1/7075

    摘要： An apparatus and method for correlating a signal over a correlation interval while accommodating spreading code frequency offset is described. In one embodiment, the apparatus includes a plurality of correlators, where each correlator forms a correlation result corresponding to a unique code frequency offset hypothesis. Each correlator selects samples from a tapped delay line at a tap position moved along the delay line at a rate corresponding to the correlator unique code frequency offset hypothesis.

    摘要翻译： 描述了一种用于在适应扩展码频率偏移的同时在相关间隔上相关信号的装置和方法。 在一个实施例中，该装置包括多个相关器，其中每个相关器形成对应于唯一代码频率偏移假设的相关结果。 每个相关器以对应于相关器唯一代码频率偏移假设的速率沿着延迟线移动的抽头位置处的抽头延迟线选择样本。

    Method and device for frame sync detection using channel combining and correlation
    7.
    发明授权
    Method and device for frame sync detection using channel combining and correlation 有权
    使用信道组合和相关的帧同步检测方法和装置

    公开(公告)号：US07130333B2

    公开(公告)日：2006-10-31

    申请号：US09995095

    申请日：2001-11-27

    申请人： Leroy Andrew Gibson, Jr. ,  Dan M. Griffin ,  Lyman D. Horne ,  Randal R. Sylvester

    发明人： Leroy Andrew Gibson, Jr. ,  Dan M. Griffin ,  Lyman D. Horne ,  Randal R. Sylvester

    IPC分类号： H04B1/707

    CPC分类号： H04B1/7075

    摘要： A method and device for frame sync detection using signal combining and correlation. The method comprises the steps of despreading PN coded signals to provide in-phase I1–In, and quadrature phase Q1–Qn signals, wherein each I1–In and each Q1–Qn signal contains at least one sync bit and n≧2. The at least one sync bit from each I1–In, and quadrature phase Q1–Qn signals are summed to form sums Is1 and Qs1, respectively. The next step provides a reference sync having at least one bit and compares each sum Is1 and Qs1 with the at least one reference bit. The results of each Is1 and Qs1 comparison are accumulated so as to form two accumulates, IA and QA, respectively. Each accumulate IA and QA, is squared to form IA2 and QA2 from which the sum IA2 and QA2 is formed. The sum IA2+QA2 is compared with a predetermined threshold and as a result of the comparison a determination of whether frame sync has been achieved is made.

    摘要翻译： 一种使用信号组合和相关的帧同步检测的方法和装置。 该方法包括以下步骤：对PN编码信号进行解扩，以提供同相I 1 -I N n N，以及正交相位Q 1 -Q 1， 其中每个I 1 -I n个和每个Q 1 -Q N n个/ N个 >信号包含至少一个同步位，n> = 2。 来自每个I 1 -I N SUB的至少一个同步位以及正交相位Q 1 -Q N n N 信号被相加以形成和分别分别为I S 1和S 2。 下一步骤提供具有至少一个比特的参考同步，并将每个和I 1和S 1和S 1＆lt; S 1＆lt;和＆lt; S 1＆lt;＆gt;和至少一个参考比特进行比较。 每个I＆lt; s1＆gt;和＆lt; s1＆lt;比较比较的结果被累积，以便形成两个累加， SUB>。 每个累加I A和A A A均被平方以形成I A 2和Q A 2， 总和2和/或2＆lt; 2＆gt;和＆lt; 2＆gt; 2＆lt; 2＆gt; 形成了。 将总和与预定阈值进行比较，并作为比较的结果。 确定是否已经实现帧同步。

    Method and apparatus to initiate communications between an unknown node and an existing secure network
    10.
    发明授权
    Method and apparatus to initiate communications between an unknown node and an existing secure network 有权
    启动未知节点与现有安全网络之间的通信的方法和装置

    公开(公告)号：US07609751B1

    公开(公告)日：2009-10-27

    申请号：US11136783

    申请日：2005-05-24

    申请人： Thomas R. Giallorenzi ,  Johnny M. Harris ,  Eric K. Hall ,  Richard B. Ertel ,  Dan M. Griffin

    发明人： Thomas R. Giallorenzi ,  Johnny M. Harris ,  Eric K. Hall ,  Richard B. Ertel ,  Dan M. Griffin

    IPC分类号： H04B1/00

    CPC分类号： H04B1/7087 ,  H04B1/7075

    摘要： A first node initiating communications with a second node already in a secure network sends a discovery burst having a preamble portion and a payload portion. The preamble portion is sent at a varying frequency between high and low thresholds that are reflective of Doppler uncertainty between the nodes. The second node continuously listens at a frequency, termed an acquisition frequency. A data sequence in the preamble portion, known to the second node, is received and used to determine the receive instant in the preamble portion, and thereby compare against the known frequency ramp to determine the frequency at which the payload portion will be received. Preferably, the first node varies the preamble portion between thresholds more than once within the time span of a single preamble portion, and the preamble and payload portions are spread with different spreading codes. The preamble portion may also be disguised with noise generated by the first node.

    摘要翻译： 发起与已经在安全网络中的第二节点的通信的第一节点发送具有前导码部分和有效载荷部分的发现脉冲串。 前导码部分以反映节点之间的多普勒不确定性的高阈值和低阈值之间的变化频率发送。 第二个节点连续以一个频率收听，称为采集频率。 在第二节点已知的前同步码部分中的数据序列被接收并用于确定前同步码部分中的接收时刻，从而与已知的频率斜坡进行比较，以确定有效负载部分将被接收的频率。 优选地，第一节点在单个前导码部分的时间跨度内多于一次地改变阈值之间的前导码部分，并且前导码和有效载荷部分以不同的扩展码扩展。 前同步码部分也可以伪装成由第一节点产生的噪声。