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21.发明授权公开(公告)号：US07269759B2
公开(公告)日：2007-09-11
申请号：US10912103
申请日：2004-08-06
申请人： Stuart David Biles
发明人： Stuart David Biles
IPC分类号： G11C29/52
CPC分类号： G06F11/004 , G06F12/0802
摘要： The present invention provides a data processing apparatus and method for handling corrupted data values. The method comprises the steps of: a) accessing a data value in a memory within a data processing apparatus; b) initiating processing of the data value within the data processing apparatus; c) whilst at least one of the steps a) and b) are being performed, determining whether the data value accessed is corrupted; and d) when it is determined that the data value is corrupted, disabling an interface used to propagate data values between the data processing apparatus and a device coupled to the data processing apparatus to prevent propagation of a corrupted data value to the device. When a data value is accessed, the data processing apparatus can begin processing of that data value and, hence, the performance of the data processing apparatus is not reduced. If it is determined that the data value which was accessed was corrupted or contains an error then the interface which couples the data processing apparatus with the device is disabled. Disabling the interface effectively quarantines any corrupted data values by preventing them from being propagated to the device. Preventing corrupted data values from being propagated to the device ensures that no change in state can occur in the device as a result of the corrupted data values.
摘要翻译： 本发明提供一种用于处理损坏的数据值的数据处理装置和方法。 该方法包括以下步骤：a）访问数据处理设备内的存储器中的数据值; b）启动数据处理装置内的数据值的处理; c）在执行步骤a）和b）中的至少一个时，确定所访问的数据值是否被破坏; 以及d）当确定数据值被破坏时，禁用用于在数据处理设备和耦合到数据处理设备的设备之间传播数据值的接口，以防止损坏的数据值传播到设备。 当访问数据值时，数据处理装置可以开始处理该数据值，因此数据处理装置的性能不会降低。 如果确定所访问的数据值被破坏或包含错误，则将数据处理设备与设备耦合的接口被禁用。 禁用接口通过防止它们传播到设备来有效隔离任何损坏的数据值。 防止损坏的数据值传播到设备，确保由于损坏的数据值，设备中不会发生状态改变。
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公开(公告)号：US08949844B2
公开(公告)日：2015-02-03
申请号：US12923276
申请日：2010-09-13
CPC分类号： G06F9/5077
摘要： A processor 6 is provided with a plurality of hardware resources, such as performance monitors 12 and context pointers 18. Boundary indicating circuitry 14, 20 stores a boundary value which is programmable and which indicates a boundary position dividing the hardware resources into a first portion and a second portion. Resource control circuitry 16, 22 controls access to the hardware resources such that when program execution circuitry 8 is executing a first program it is responsive to a query as to how many off said plurality of hardware resources are present to return a first value whereas when the program execution circuitry is executing a second program it responds to such a query by returning a value corresponding to those hardware resources within the second portion.
摘要翻译： 处理器6具有诸如性能监视器12和上下文指针18之类的多个硬件资源。边界指示电路14,20存储可编程的边界值，其指示将硬件资源分成第一部分的边界位置， 第二部分。 资源控制电路16,22控制对硬件资源的访问，使得当程序执行电路8正在执行第一程序时，它响应于关于多少个所述多个硬件资源出现以返回第一值的查询，而当 程序执行电路正在执行第二程序，它通过返回与第二部分内的这些硬件资源相对应的值来响应于这样的查询。
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公开(公告)号：US08589631B2
公开(公告)日：2013-11-19
申请号：US13137780
申请日：2011-09-12
IPC分类号： G06F12/00
CPC分类号： G06F12/0833 , Y02D10/13
摘要： Interconnect circuitry configured to provide routes for interconnecting several initiator devices and at least one recipient device including a memory. At least one of the initiator devices has a cache for storing a local copy of a subset of data items stored in the memory. The interconnect circuitry includes: a plurality of input ports and at least one output port; a plurality of paths for transmitting the transaction requests between the inputs and the at least one output; coherency control circuitry for maintaining an order in which at least some of the transaction requests to a same data storage location proceed through the interconnect circuitry. The interconnect circuitry is configured not to control the writeback transaction requests with the coherency control circuitry, such that the writeback transaction requests proceed independently of transaction requests routed through the coherency control circuitry.
摘要翻译： 互连电路，被配置为提供用于互连多个发起者设备和至少一个包括存储器的接收设备的路由。 至少一个启动器设备具有用于存储存储在存储器中的数据项的子集的本地副本的高速缓存。 所述互连电路包括：多个输入端口和至少一个输出端口; 用于在所述输入和所述至少一个输出之间传送交易请求的多个路径; 一致性控制电路，用于维持其中至少一些交易请求到同一数据存储位置的顺序通过互连电路进行。 互连电路被配置为不利用一致性控制电路控制回写事务请求，使得回写事务请求独立于通过一致性控制电路路由的事务请求而进行。
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公开(公告)号：US20130013889A1
公开(公告)日：2013-01-10
申请号：US13067912
申请日：2011-07-06
IPC分类号： G06F12/10
CPC分类号： G06F12/1483 , G06F12/02 , G06F12/1045 , G06F12/109 , G06F12/121
摘要： A memory management unit includes a translation buffer unit for storing memory management attribute entries that originate from a plurality of different memory management contexts. Context disambiguation circuitry responds to one or more characteristics of a received memory transaction to form a stream identifier and to determine which of the memory management context matches that memory transaction. In this way, memory management attribute entries stored within the translation lookaside buffer are formed under control of the appropriate matching context. When the translation buffer unit receives a further transaction, then a further stream identifier is formed therefrom and if this matches the stream identifier of stored memory management attribute entries then those memory management attribute entries may be used (if appropriate) for that further memory transaction.
摘要翻译： 存储器管理单元包括用于存储来自多个不同存储器管理上下文的存储器管理属性条目的翻译缓冲器单元。 上下文消歧电路响应于所接收的存储器事务的一个或多个特性以形成流标识符并且确定哪个存储器管理上下文与该存储器事务匹配。 以这种方式，在适当的匹配上下文的控制下形成存储在翻译后备缓冲器内的存储器管理属性条目。 当翻译缓冲器单元接收到另外的事务时，则从其形成另外的流标识符，并且如果这与存储的存储器管理属性条目的流标识符相匹配，则可以使用那些存储器管理属性条目（如果适用）用于该另外的存储器事务。
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公开(公告)号：US20120079211A1
公开(公告)日：2012-03-29
申请号：US13137780
申请日：2011-09-12
IPC分类号： G06F12/08
CPC分类号： G06F12/0833 , Y02D10/13
摘要： Interconnect circuitry configured to provide routes for interconnecting several initiator devices and at least one recipient device including a memory. At least one of the initiator devices has a cache for storing a local copy of a subset of data items stored in the memory. The interconnect circuitry includes: a plurality of input ports and at least one output port; a plurality of paths for transmitting the transaction requests between the inputs and the at least one output; coherency control circuitry for maintaining an order in which at least some of the transaction requests to a same data storage location proceed through the interconnect circuitry. The interconnect circuitry is configured not to control the writeback transaction requests with the coherency control circuitry, such that the writeback transaction requests proceed independently of transaction requests routed through the coherency control circuitry.
摘要翻译： 互连电路，被配置为提供用于互连多个发起者设备和至少一个包括存储器的接收设备的路由。 至少一个启动器设备具有用于存储存储在存储器中的数据项的子集的本地副本的高速缓存。 所述互连电路包括：多个输入端口和至少一个输出端口; 用于在所述输入和所述至少一个输出之间传送交易请求的多个路径; 一致性控制电路，用于维持其中至少一些交易请求到同一数据存储位置的顺序通过互连电路进行。 互连电路被配置为不利用一致性控制电路控制回写事务请求，使得回写事务请求独立于通过一致性控制电路路由的事务请求而进行。
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公开(公告)号：US08001331B2
公开(公告)日：2011-08-16
申请号：US12081583
申请日：2008-04-17
IPC分类号： G06F12/00
CPC分类号： G06F12/0804 , G06F12/0215 , G06F12/121 , G06F12/127
摘要： A processing system 1 including a memory 10 and a cache memory 4 is provided with a page status unit 40 for providing a cache controller with a page open indication indicating one or more open pages of data values in memory. At least one of one or more cache management operations performed by the cache controller is responsive to the page open indication so that the efficiency and/or speed of the processing system can be improved.
摘要翻译： 包括存储器10和高速缓存存储器4的处理系统1设置有页面状态单元40，用于向高速缓存控制器提供指示存储器中数据值的一个或多个打开页面的页面打开指示。 高速缓存控制器执行的一个或多个高速缓存管理操作中的至少一个响应于页面打开指示，从而可以提高处理系统的效率和/或速度。
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公开(公告)号：US20110093750A1
公开(公告)日：2011-04-21
申请号：US12923276
申请日：2010-09-13
CPC分类号： G06F9/5077
摘要： A processor 6 is provided with a plurality of hardware resources, such as performance monitors 12 and context pointers 18. Boundary indicating circuitry 14, 20 stores a boundary value which is programmable and which indicates a boundary position dividing the hardware resources into a first portion and a second portion. Resource control circuitry 16, 22 controls access to the hardware resources such that when program execution circuitry 8 is executing a first program it is responsive to a query as to how many off said plurality of hardware resources are present to return a first value whereas when the program execution circuitry is executing a second program it responds to such a query by returning a value corresponding to those hardware resources within the second portion.
摘要翻译： 处理器6具有诸如性能监视器12和上下文指针18之类的多个硬件资源。边界指示电路14,20存储可编程的边界值，其指示将硬件资源分成第一部分的边界位置， 第二部分。 资源控制电路16,22控制对硬件资源的访问，使得当程序执行电路8正在执行第一程序时，它响应于关于多少个所述多个硬件资源出现以返回第一值的查询，而当 程序执行电路正在执行第二程序，它通过返回与第二部分内的这些硬件资源相对应的值来响应于这样的查询。
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公开(公告)号：US07877587B2
公开(公告)日：2011-01-25
申请号：US11449858
申请日：2006-06-09
CPC分类号： G06F9/3851 , G06F9/30101 , G06F9/3848
摘要： A branch prediction mechanism 16, 18 within a multithreaded processor having hardware scheduling logic 6, 8, 10, 12 uses a shared global history table 18 which is indexed by respective branch history registers 20, 22 for each program thread. Different mappings are used between preceding branch behavior and the prediction value stored within respective branch history registers 20, 22. These different mappings may be provided by inverters placed into the shift in paths for the branch history registers 20, 22 or by adders 40, 42 or in some other way. The different mappings help to equalise the probability of use of the particular storage locations within the global history table 18 such that the plurality of program threads are not competing excessively for the same storage locations corresponding to the more commonly occurring patterns of preceding branch behavior.
摘要翻译： 具有硬件调度逻辑6,8,10,12的多线程处理器内的分支预测机制16,18使用共享全局历史表18，该共享全局历史表18由各个分支历史寄存器20,22针对每个程序线索引。 在先前的分支行为和存储在相应的分支历史寄存器20,22中的预测值之间使用不同的映射。这些不同的映射可以由放置在分支历史寄存器20,22的路径中的反相器或由加法器40,42 或以其他方式。 不同的映射有助于使全局历史表18中的特定存储位置的使用概率相等，使得多个程序线程对于与先前分支行为的更常见的模式相对应的相同存储位置不会过度竞争。
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公开(公告)号：US07769955B2
公开(公告)日：2010-08-03
申请号：US11790811
申请日：2007-04-27
申请人： Emre Özer , Stuart David Biles
发明人： Emre Özer , Stuart David Biles
IPC分类号： G06F12/00
CPC分类号： G06F12/0811 , G06F9/3802 , G06F9/3851 , G06F12/0897
摘要： A data processing apparatus is provided wherein processing circuitry executes multiple program threads including at least one high priority thread and at least one lower priority thread. Instructions required by the threads are retrieved from a cache memory hierarchy comprising multiple cache levels. The cache memory hierarchy includes a bypass path for omitting a predetermined level of the cache memory hierarchy when performing a lookup procedure for a required instruction and for bypassing said predetermined level of the cache memory hierarchy when returning said required instruction to said processing circuitry. The bypass path is used by default when the requested instruction is for a lower priority thread.
摘要翻译： 提供了一种数据处理装置，其中处理电路执行包括至少一个高优先级线程和至少一个较低优先级线程的多个程序线程。 从包含多个高速缓存级别的缓存存储器层次中检索线程所需的指令。 所述高速缓存存储器层级包括旁路路径，用于在执行所需指令的查找过程时省略所述高速缓存存储器层级的预定级别，以及当将所述所需指令返回给所述处理电路时绕过所述高速缓存存储器层级的所述预定级别。 当请求的指令用于较低优先级的线程时，默认使用旁路路径。
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30.发明申请公开(公告)号：US20080282067A1
公开(公告)日：2008-11-13
申请号：US12078100
申请日：2008-03-27
申请人： Emre Ozer , Stuart David Biles
发明人： Emre Ozer , Stuart David Biles
IPC分类号： G06F9/30
CPC分类号： G06F9/3851 , G06F9/4881
摘要： A multi-threaded in-order superscalar processor 2 includes an issue stage 12 including issue circuitry 22, 24 for selecting instructions to be issued to execution units 14, 16 in dependence upon a currently selected issue policy. A plurality of different issue policies are provided by associated different policy circuitry 28, 30, 32 and a selection between which of these instances of the policy circuitry 28, 30, 32 is active is made by policy selecting circuitry 34 in dependence upon detected dynamic behaviour of the processor 2.
摘要翻译： 多线程顺序超标量处理器2包括发行阶段12，其包括发行电路22,24，用于根据当前选择的发行策略来选择要发布到执行单元14,16的指令。 多个不同的问题策略由相关联的不同策略电路28,30,32提供，并且策略电路28,30,32的这些实例中的哪一个被选择是由策略选择电路34根据检测到的动态行为 的处理器2。
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