公开(公告)号：US20090319707A1

公开(公告)日：2009-12-24

申请号：US12213470

申请日：2008-06-19

申请人： Christopher William Laycock ,  Antony John Harris ,  Bruce James Mathewson ,  Richard Roy Grisenthwaite ,  Stuart David Biles

发明人： Christopher William Laycock ,  Antony John Harris ,  Bruce James Mathewson ,  Richard Roy Grisenthwaite ,  Stuart David Biles

IPC分类号： G06F13/40

CPC分类号： G06F13/4221

摘要： An integrated circuit 2 includes a transaction master 4 connected via interconnect circuitry 10 to a transaction slave 12. The transaction slave 12 generates a transfer-complete signal (R Last or B) to indicate completion of a data transfer (either a read or a write). When this transfer-complete signal has been received by the transaction master 4, then the transaction master 4 generates a complete-acknowledgement signal RACK, WACK, which is passed back to the transaction slave so as to acknowledge receipt of the transfer-complete signal.

摘要翻译： 集成电路2包括经由互连电路10连接到交易从属单元12的交易主机4.交易从机12产生传输完成信号（R Last或B）以指示完成数据传送（读或写 ）。 当该传输完成信号已被交易主机4接收到时，交易主机4产生一个完整确认信号RACK，其返回到交易从属单元，以便确认传送完成信号的接收。

公开(公告)号：US20090216958A1

公开(公告)日：2009-08-27

申请号：US12071505

申请日：2008-02-21

申请人： Stuart David Biles ,  Nigel Charles Paver ,  Chander Sudanthi

发明人： Stuart David Biles ,  Nigel Charles Paver ,  Chander Sudanthi

IPC分类号： G06F13/40

CPC分类号： G06F13/1668 ,  G06F2213/0038

摘要： A data processing system in the form of an integrated circuit 2 includes a general purpose programmable processor 4 and a hardware accelerator 6. A shared memory management unit 10 provides memory management operations on behalf of both of the processor core 4 and the hardware accelerator 6. The processor 4 and the hardware accelerator 6 share a memory system 8. A first communication channel 12 between the processor 4 and the hardware accelerator 6 communicates at least control signals therebetween. A second communication channel 14 coupling the hardware accelerator 6 and the memory system 8 allows the hardware accelerator 6 to perform its own data access operations upon the memory system 8.

摘要翻译： 集成电路2形式的数据处理系统包括通用可编程处理器4和硬件加速器6.共享存储器管理单元10代表处理器核心4和硬件加速器6两者提供存储器管理操作。 处理器4和硬件加速器6共享存储器系统8.处理器4和硬件加速器6之间的第一通信信道12至少在其间通信控制信号。 耦合硬件加速器6和存储器系统8的第二通信通道14允许硬件加速器6在存储器系统8上执行其自己的数据访问操作。

公开(公告)号：US20090150620A1

公开(公告)日：2009-06-11

申请号：US12000005

申请日：2007-12-06

申请人： Nigel Charles Paver ,  Stuart David Biles

发明人： Nigel Charles Paver ,  Stuart David Biles

IPC分类号： G06F12/08

CPC分类号： G06F12/0804 ,  G06F9/3879 ,  G06F12/0815 ,  G06F12/1027

摘要： A data processing apparatus 2 includes a programmable general purpose processor 10 coupled to a hardware accelerator 12. A memory system 14, 6, 8 is shared by the processor 10 and the hardware accelerator 12. Memory system monitoring circuitry 16 is responsive to one or more predetermined operations performed by the processor 10 upon the memory system 14, 6, 8 to generate a trigger to the hardware accelerator 12 for it to halt its processing operations and clean any data values held as temporary variables within registers 20 of the hardware accelerator back to the memory system 14, 6, 8.

摘要翻译： 数据处理装置2包括耦合到硬件加速器12的可编程通用处理器10.存储器系统14,6,8由处理器10和硬件加速器12共享。存储器系统监视电路16响应于一个或多个 由处理器10在存储器系统14,6,8上执行的预定操作，以产生对硬件加速器12的触发，以使其停止其处理操作，并清除作为硬件加速器的寄存器20内的临时变量所保持的任何数据值。 存储器系统14,6,8。

公开(公告)号：US20080040546A1

公开(公告)日：2008-02-14

申请号：US11503410

申请日：2006-08-14

申请人： Vladimir Vasekin ,  Stuart David Biles

发明人： Vladimir Vasekin ,  Stuart David Biles

IPC分类号： G06F12/00

CPC分类号： G06F12/0884 ,  G06F2212/1028 ,  Y02D10/13

摘要： A data processing apparatus and method are provided for performing a cache lookup in an energy efficient manner. The data processing apparatus has at least one processing unit for performing operations and a cache having a plurality of cache lines for storing data values for access by that at least one processing unit when performing those operations. The at least one processing unit provides a plurality of sources from which access requests are issued to the cache, and each access request, in addition to specifying an address, further includes a source identifier indicating the source of the access request. A storage element is provided for storing for each source an indication as to whether the last access request from that source resulted in a hit in the cache, and cache line identification logic determines, for each access request, whether that access request is seeking to access the same cache line as the last access request issued by that source. The cache control logic is operable when handling an access request to constrain the lookup procedure to only a subset of the storage blocks within the cache if it is determined that the access request is to the same cache line as the last access request issued by the relevant source, and the storage element indicates that the last access request from that source resulted in a hit in the cache. This yields significant energy savings when accessing the cache.

摘要翻译： 提供了一种以能量效率方式执行高速缓存查找的数据处理装置和方法。 所述数据处理装置具有用于执行操作的至少一个处理单元和具有多个高速缓存行的高速缓存，所述高速缓存行用于在执行所述操作时存储由所述至少一个处理单元访问的数据值。 所述至少一个处理单元提供多个源，从所述多个源向所述高速缓存发出访问请求，并且除了指定地址之外，每个访问请求还包括指示所述访问请求的源的源标识符。 提供存储元件，用于为每个源存储关于来自该源的最后访问请求是否导致高速缓存中的命中的指示，并且高速缓存行标识逻辑针对每个访问请求确定该访问请求是否正在寻求访问 与该源发出的最后访问请求相同的高速缓存行。 如果确定访问请求与由相关的最后访问请求发送到相同的高速缓存行，则处理访问请求以将查找过程限制为仅在缓存内的存储块的子集的情况下，高速缓存控制逻辑可操作 源，并且存储元素指示来自该源的最后访问请求导致高速缓存中的命中。 这在访问缓存时可以节省大量能源。

公开(公告)号：US07269759B2

公开(公告)日：2007-09-11

申请号：US10912103

申请日：2004-08-06

申请人： Stuart David Biles

发明人： Stuart David Biles

IPC分类号： G11C29/52

CPC分类号： G06F11/004 ,  G06F12/0802

摘要： The present invention provides a data processing apparatus and method for handling corrupted data values. The method comprises the steps of: a) accessing a data value in a memory within a data processing apparatus; b) initiating processing of the data value within the data processing apparatus; c) whilst at least one of the steps a) and b) are being performed, determining whether the data value accessed is corrupted; and d) when it is determined that the data value is corrupted, disabling an interface used to propagate data values between the data processing apparatus and a device coupled to the data processing apparatus to prevent propagation of a corrupted data value to the device. When a data value is accessed, the data processing apparatus can begin processing of that data value and, hence, the performance of the data processing apparatus is not reduced. If it is determined that the data value which was accessed was corrupted or contains an error then the interface which couples the data processing apparatus with the device is disabled. Disabling the interface effectively quarantines any corrupted data values by preventing them from being propagated to the device. Preventing corrupted data values from being propagated to the device ensures that no change in state can occur in the device as a result of the corrupted data values.

摘要翻译： 本发明提供一种用于处理损坏的数据值的数据处理装置和方法。 该方法包括以下步骤：a）访问数据处理设备内的存储器中的数据值; b）启动数据处理装置内的数据值的处理; c）在执行步骤a）和b）中的至少一个时，确定所访问的数据值是否被破坏; 以及d）当确定数据值被破坏时，禁用用于在数据处理设备和耦合到数据处理设备的设备之间传播数据值的接口，以防止损坏的数据值传播到设备。 当访问数据值时，数据处理装置可以开始处理该数据值，因此数据处理装置的性能不会降低。 如果确定所访问的数据值被破坏或包含错误，则将数据处理设备与设备耦合的接口被禁用。 禁用接口通过防止它们传播到设备来有效隔离任何损坏的数据值。 防止损坏的数据值传播到设备，确保由于损坏的数据值，设备中不会发生状态改变。

公开(公告)号：US08949844B2

公开(公告)日：2015-02-03

申请号：US12923276

申请日：2010-09-13

申请人： Michael John Williams ,  Stuart David Biles

发明人： Michael John Williams ,  Stuart David Biles

IPC分类号： G06F9/455 ,  G06F9/46 ,  G06F7/04 ,  G06F13/00 ,  G06F9/50

CPC分类号： G06F9/5077

摘要： A processor 6 is provided with a plurality of hardware resources, such as performance monitors 12 and context pointers 18. Boundary indicating circuitry 14, 20 stores a boundary value which is programmable and which indicates a boundary position dividing the hardware resources into a first portion and a second portion. Resource control circuitry 16, 22 controls access to the hardware resources such that when program execution circuitry 8 is executing a first program it is responsive to a query as to how many off said plurality of hardware resources are present to return a first value whereas when the program execution circuitry is executing a second program it responds to such a query by returning a value corresponding to those hardware resources within the second portion.

摘要翻译： 处理器6具有诸如性能监视器12和上下文指针18之类的多个硬件资源。边界指示电路14,20存储可编程的边界值，其指示将硬件资源分成第一部分的边界位置， 第二部分。 资源控制电路16,22控制对硬件资源的访问，使得当程序执行电路8正在执行第一程序时，它响应于关于多少个所述多个硬件资源出现以返回第一值的查询，而当 程序执行电路正在执行第二程序，它通过返回与第二部分内的这些硬件资源相对应的值来响应于这样的查询。

公开(公告)号：US08589631B2

公开(公告)日：2013-11-19

申请号：US13137780

申请日：2011-09-12

申请人： Christopher William Laycock ,  Antony John Harris ,  Bruce James Mathewson ,  Stuart David Biles

发明人： Christopher William Laycock ,  Antony John Harris ,  Bruce James Mathewson ,  Stuart David Biles

IPC分类号： G06F12/00

CPC分类号： G06F12/0833 ,  Y02D10/13

摘要： Interconnect circuitry configured to provide routes for interconnecting several initiator devices and at least one recipient device including a memory. At least one of the initiator devices has a cache for storing a local copy of a subset of data items stored in the memory. The interconnect circuitry includes: a plurality of input ports and at least one output port; a plurality of paths for transmitting the transaction requests between the inputs and the at least one output; coherency control circuitry for maintaining an order in which at least some of the transaction requests to a same data storage location proceed through the interconnect circuitry. The interconnect circuitry is configured not to control the writeback transaction requests with the coherency control circuitry, such that the writeback transaction requests proceed independently of transaction requests routed through the coherency control circuitry.

摘要翻译： 互连电路，被配置为提供用于互连多个发起者设备和至少一个包括存储器的接收设备的路由。 至少一个启动器设备具有用于存储存储在存储器中的数据项的子集的本地副本的高速缓存。 所述互连电路包括：多个输入端口和至少一个输出端口; 用于在所述输入和所述至少一个输出之间传送交易请求的多个路径; 一致性控制电路，用于维持其中至少一些交易请求到同一数据存储位置的顺序通过互连电路进行。 互连电路被配置为不利用一致性控制电路控制回写事务请求，使得回写事务请求独立于通过一致性控制电路路由的事务请求而进行。

公开(公告)号：US20130013889A1

公开(公告)日：2013-01-10

申请号：US13067912

申请日：2011-07-06

申请人： Jaikumar Devaraj ,  Viswanath Chakrala ,  Stuart David Biles ,  Shrilola Chitrapadi

发明人： Jaikumar Devaraj ,  Viswanath Chakrala ,  Stuart David Biles ,  Shrilola Chitrapadi

IPC分类号： G06F12/10

CPC分类号： G06F12/1483 ,  G06F12/02 ,  G06F12/1045 ,  G06F12/109 ,  G06F12/121

摘要： A memory management unit includes a translation buffer unit for storing memory management attribute entries that originate from a plurality of different memory management contexts. Context disambiguation circuitry responds to one or more characteristics of a received memory transaction to form a stream identifier and to determine which of the memory management context matches that memory transaction. In this way, memory management attribute entries stored within the translation lookaside buffer are formed under control of the appropriate matching context. When the translation buffer unit receives a further transaction, then a further stream identifier is formed therefrom and if this matches the stream identifier of stored memory management attribute entries then those memory management attribute entries may be used (if appropriate) for that further memory transaction.

摘要翻译： 存储器管理单元包括用于存储来自多个不同存储器管理上下文的存储器管理属性条目的翻译缓冲器单元。 上下文消歧电路响应于所接收的存储器事务的一个或多个特性以形成流标识符并且确定哪个存储器管理上下文与该存储器事务匹配。 以这种方式，在适当的匹配上下文的控制下形成存储在翻译后备缓冲器内的存储器管理属性条目。 当翻译缓冲器单元接收到另外的事务时，则从其形成另外的流标识符，并且如果这与存储的存储器管理属性条目的流标识符相匹配，则可以使用那些存储器管理属性条目（如果适用）用于该另外的存储器事务。

公开(公告)号：US20120079211A1

公开(公告)日：2012-03-29

申请号：US13137780

申请日：2011-09-12

申请人： Christopher William Laycock ,  Antony John Harris ,  Bruce James Mathewson ,  Stuart David Biles

发明人： Christopher William Laycock ,  Antony John Harris ,  Bruce James Mathewson ,  Stuart David Biles

IPC分类号： G06F12/08

CPC分类号： G06F12/0833 ,  Y02D10/13

摘要： Interconnect circuitry configured to provide routes for interconnecting several initiator devices and at least one recipient device including a memory. At least one of the initiator devices has a cache for storing a local copy of a subset of data items stored in the memory. The interconnect circuitry includes: a plurality of input ports and at least one output port; a plurality of paths for transmitting the transaction requests between the inputs and the at least one output; coherency control circuitry for maintaining an order in which at least some of the transaction requests to a same data storage location proceed through the interconnect circuitry. The interconnect circuitry is configured not to control the writeback transaction requests with the coherency control circuitry, such that the writeback transaction requests proceed independently of transaction requests routed through the coherency control circuitry.

摘要翻译： 互连电路，被配置为提供用于互连多个发起者设备和至少一个包括存储器的接收设备的路由。 至少一个启动器设备具有用于存储存储在存储器中的数据项的子集的本地副本的高速缓存。 所述互连电路包括：多个输入端口和至少一个输出端口; 用于在所述输入和所述至少一个输出之间传送交易请求的多个路径; 一致性控制电路，用于维持其中至少一些交易请求到同一数据存储位置的顺序通过互连电路进行。 互连电路被配置为不利用一致性控制电路控制回写事务请求，使得回写事务请求独立于通过一致性控制电路路由的事务请求而进行。

公开(公告)号：US08001331B2

公开(公告)日：2011-08-16

申请号：US12081583

申请日：2008-04-17

申请人： Stuart David Biles ,  Nigel Charles Paver ,  Chander Sudanthi ,  Timothy Charles Mace

发明人： Stuart David Biles ,  Nigel Charles Paver ,  Chander Sudanthi ,  Timothy Charles Mace

IPC分类号： G06F12/00

CPC分类号： G06F12/0804 ,  G06F12/0215 ,  G06F12/121 ,  G06F12/127

摘要： A processing system 1 including a memory 10 and a cache memory 4 is provided with a page status unit 40 for providing a cache controller with a page open indication indicating one or more open pages of data values in memory. At least one of one or more cache management operations performed by the cache controller is responsive to the page open indication so that the efficiency and/or speed of the processing system can be improved.

摘要翻译： 包括存储器10和高速缓存存储器4的处理系统1设置有页面状态单元40，用于向高速缓存控制器提供指示存储器中数据值的一个或多个打开页面的页面打开指示。 高速缓存控制器执行的一个或多个高速缓存管理操作中的至少一个响应于页面打开指示，从而可以提高处理系统的效率和/或速度。