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21.发明授权Circuit for minimizing filter capacitance leakage induced jitter in phase locked loops (PPLs) 有权用于最小化锁相环（PPL）中的滤波电容泄漏引起的抖动的电路公开(公告)号：US07132896B2
公开(公告)日：2006-11-07
申请号：US10981155
申请日：2004-11-04
CPC分类号： H03L7/0893 , H03L7/093 , H03L7/095
摘要： A method, an apparatus, and a computer program are provided to minimize filter capacitor leakage in a Phased Locked Loop (PLL). In high frequency processors and devices, filter leakage currents can cause substantial problems by causing PLLs to drift out of phase lock. To combat the leakage currents, a dummy filter and other components are employed to provide additional charge or voltage to a low pass filter during lock. The provision of the charge or voltage exponentially decreases the rate of decay of voltage across the low pass filter caused by leakage currents.
摘要翻译： 提供了一种方法，装置和计算机程序以最小化相位锁定环（PLL）中的滤波电容器泄漏。 在高频处理器和器件中，滤波器漏电流可能会导致相位锁相位漂移出现相当大的问题。 为了防止泄漏电流，使用虚拟滤波器和其他组件在锁定期间向低通滤波器提供额外的充电或电压。 充电或电压的提供以指数方式降低由漏电流引起的低通滤波器的电压衰减速率。
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22.发明授权System and method for on/off-chip characterization of pulse-width limiter outputs 失效用于脉宽限幅器输出的片外特性的系统和方法公开(公告)号：US08054119B2
公开(公告)日：2011-11-08
申请号：US11109090
申请日：2005-04-19
IPC分类号： H03K3/017
CPC分类号： H03K5/156 , G01R31/31708 , G01R31/31725 , H03K5/05 , H03K5/26
摘要： The present invention provides for a method for characterization of pulse-width limiter outputs. A known clock signal is received. A pulse width of the received known clock signal is limited through a first pulse-width limiter to generate a first intermediate signal. The first intermediate signal is delayed by a known amount to generate a first delayed signal. The first intermediate signal is inverted to generate a first inverted signal. A pulse width of the first inverted signal is limited through a second pulse-width limiter to generate a second intermediate signal. The second intermediate signal is delayed by a known amount to generate a second delayed signal. A logic OR operation is performed on the first delayed signal and the second delayed signal to generate a clock out signal.
摘要翻译： 本发明提供了用于表征脉冲宽度限制器输出的方法。 接收已知的时钟信号。 所接收的已知时钟信号的脉冲宽度通过第一脉冲宽度限制器来限制，以产生第一中间信号。 第一中间信号被延迟已知的量以产生第一延迟信号。 第一中间信号被反相以产生第一反相信号。 通过第二脉冲宽度限幅器限制第一反相信号的脉冲宽度以产生第二中间信号。 第二中间信号被延迟已知的量以产生第二延迟信号。 对第一延迟信号和第二延迟信号执行逻辑或运算以产生时钟输出信号。
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公开(公告)号：US07617059B2
公开(公告)日：2009-11-10
申请号：US11931879
申请日：2007-10-31
CPC分类号： G01R29/02 , G01R31/31725 , G01R31/31726
摘要： The disclosed methodology and apparatus measures the duty cycle of a clock signal. A variable duty cycle circuit receives a clock signal from a clock signal generator. The variable duty cycle circuit adjusts the duty cycle of the clock signal by an amount dependent on a duty cycle index value that it receives. The variable duty cycle circuit supplies a duty-cycle adjusted clock signal to a divider circuit. The apparatus sweeps the frequency of the clock signal from a starting value up to a maximum frequency above which the divider circuit fails. The apparatus then determines the duty cycle of the duty-cycle adjusted clock signal from the maximum frequency.
摘要翻译： 所公开的方法和装置测量时钟信号的占空比。 可变占空比电路从时钟信号发生器接收时钟信号。 可变占空比电路根据其接收的占空比指数值来调整时钟信号的占空比。 可变占空比电路将占空比调整的时钟信号提供给分频器电路。 该装置将时钟信号的频率从起始值扫描到高于分频器电路故障的最大频率。 然后，该装置从最大频率确定占空比调整的时钟信号的占空比。
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24.发明授权Information handling system capable of detecting frequency lock of signals downstream from a signal synthesized by frequency synthesizer 失效信号处理系统能够检测由频率合成器合成的信号下行信号的频率锁定公开(公告)号：US07590194B2
公开(公告)日：2009-09-15
申请号：US11236834
申请日：2005-09-27
IPC分类号： H03D3/18
摘要： An information handling system including a frequency synthesizer lock detection system is disclosed that distributes a frequency synthesizer output signal across a distribution network to one or more receptor circuits. The distribution network may exhibit delay and other distortion that may cause the downstream signal arriving at the receptor circuit to lose frequency lock with both the frequency synthesizer output signal and a reference clock signal that controls the frequency of the synthesizer output signal. The lock detection system tests the downstream signal to determine if the downstream signal exhibits a lock with respect to the reference clock that determines the operating frequency of the frequency synthesizer. In this manner, lock of the downstream signal to the reference clock signal may be accurately assessed in one embodiment.
摘要翻译： 公开了一种包括频率合成器锁定检测系统的信息处理系统，其将分频网络上的频率合成器输出信号分配到一个或多个接收器电路。 分配网络可能表现出延迟和其他失真，这些失真可能导致下游信号到达接收器电路，同时使用频率合成器输出信号和控制合成器输出信号频率的参考时钟信号来失去频率锁定。 锁定检测系统测试下行信号以确定下游信号是否相对于确定频率合成器的工作频率的参考时钟呈现锁定。 以这种方式，可以在一个实施例中精确地评估下行信号到参考时钟信号的锁定。
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公开(公告)号：US07420400B2
公开(公告)日：2008-09-02
申请号：US11380982
申请日：2006-05-01
IPC分类号： H03K3/017
CPC分类号： G01R31/31727 , G01R31/3004 , G01R31/31726
摘要： The disclosed methodology and apparatus measures the duty cycle of a reference clock signal that a clock circuit supplies to a duty cycle measurement (DCM) circuit located “on-chip”, namely on an integrated circuit (IC) in which the DCM circuit is incorporated. In one embodiment, the DCM circuit includes a capacitor driven by a charge pump. The reference clock signal drives the charge pump. The clock circuit varies the duty cycle of the reference clock signal among a number of known duty cycle values. The DCM circuit stores resultant capacitor voltage values corresponding to each of the known duty cycle values in a data store. The DCM circuit applies a test clock signal having an unknown duty cycle to the capacitor via the charge pump, thus charging the capacitor to a new voltage value that corresponds to the duty cycle of the test clock signal. Control software accesses the data store to determine the duty cycle to which the test clock signal corresponds.
摘要翻译： 所公开的方法和装置测量时钟电路提供给位于“片上”的占空比测量（DCM）电路的参考时钟信号的占空比，即集成电路（IC），其中并入DCM电路 。 在一个实施例中，DCM电路包括由电荷泵驱动的电容器。 参考时钟信号驱动电荷泵。 时钟电路在多个已知的占空比值之间改变参考时钟信号的占空比。 DCM电路将对应于每个已知占空比值的合成电容电压值存储在数据存储器中。 DCM电路通过电荷泵向电容器施加具有未知占空比的测试时钟信号，从而将电容器充电到对应于测试时钟信号占空比的新电压值。 控制软件访问数据存储，以确定测试时钟信号对应的占空比。
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公开(公告)号：US20080122495A1
公开(公告)日：2008-05-29
申请号：US12028249
申请日：2008-02-08
IPC分类号： H03K5/22
CPC分类号： G06F1/26
摘要： A voltage calibration system includes three main units, which are a voltage level trimming unit, a trim detection unit, and a trim control unit. The three units work in conjunction with each other during a trimming operation in order to identify a tap voltage that is closest to a target voltage. In one embodiment, the voltage calibration system may be used to calibrate a voltage regulator. Upon commencement of calibration, the voltage regulator's feedback loop is open, and the target voltage is selected as the input for the feedback port of the amplifier. The voltage regulator serves as a voltage comparator that compares each tap voltage to the target voltage. When the calibration is complete, regulator's feedback loop is closed and the closest tap voltage to the target voltage is used as the regulator's input.
摘要翻译： 电压校准系统包括三个主要单元，它们是电压调整单元，微调检测单元和微调控制单元。 三个单元在微调操作期间相互协调工作，以便识别最接近目标电压的抽头电压。 在一个实施例中，电压校准系统可用于校准电压调节器。 校准开始后，电压调节器的反馈回路打开，目标电压被选为放大器反馈端口的输入。 电压调节器用作将每个抽头电压与目标电压进行比较的电压比较器。 当校准完成时，调节器的反馈回路闭合，并将最接近目标电压的分接电压用作调节器的输入。
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27.发明申请Method and Apparatus for Measuring the Relative Duty Cycle of a Clock Signal 有权用于测量时钟信号的相对占空比的方法和装置公开(公告)号：US20070271068A1
公开(公告)日：2007-11-22
申请号：US11555018
申请日：2006-10-31
申请人： David William Boerstler , Eskinder Hailu , Jieming Qi , Bin Wan
发明人： David William Boerstler , Eskinder Hailu , Jieming Qi , Bin Wan
CPC分类号： G01R31/31922 , G01R29/0273 , G01R31/31725 , G01R31/31727
摘要： In one embodiment, the disclosed methodology and apparatus measure relative duty cycle information of a clock signal with respect to an input node as the clock signal travels to selected nodes of a clock distribution network on an electronic circuit.
摘要翻译： 在一个实施例中，当时钟信号传播到电子电路上的时钟分配网络的选定节点时，所公开的方法和装置测量相对于输入节点的时钟信号的相对占空比信息。
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28.发明申请Level shifter system and method to minimize duty cycle error due to voltage differences across power domains 失效电平移位器系统和方法，可以最大限度地减少跨越电源域的电压差造成的占空比误差公开(公告)号：US20070075764A1
公开(公告)日：2007-04-05
申请号：US11242670
申请日：2005-10-04
申请人： David Boerstler , Eskinder Hailu , Kazuhiko Miki , Jieming Qi
发明人： David Boerstler , Eskinder Hailu , Kazuhiko Miki , Jieming Qi
IPC分类号： H03L5/00
CPC分类号： H03K19/00384 , H03K5/1565 , H03K19/00323 , H03K19/00369 , H03K19/0175
摘要： The present invention provides for a system comprising a first stable voltage module configured to receive a first power supply from a first power supply domain and to generate a first stable voltage in response to the received first power supply. A second stable voltage module is configured to receive a second power supply from a second power supply domain and to generate a second stable voltage in response to the received second power supply. A first set of resistors is coupled to the first stable voltage module and configured in parallel. A second set of resistors is coupled to the second stable voltage module and configured in parallel. A set of capacitors is coupled in parallel to the first set of resistors and the second set of resistors and a plurality of level shifters are coupled to the second set of resistors.
摘要翻译： 本发明提供了一种系统，其包括第一稳定电压模块，其被配置为从第一电源域接收第一电源并且响应于所接收的第一电源产生第一稳定电压。 第二稳定电压模块被配置为从第二电源域接收第二电源并且响应于所接收的第二电源产生第二稳定电压。 第一组电阻器耦合到第一稳定电压模块并且并联配置。 第二组电阻器耦合到第二稳定电压模块并且并联配置。 一组电容器并联耦合到第一组电阻器，并且第二组电阻器和多个电平移位器耦合到第二组电阻器。
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公开(公告)号：US20080111604A1
公开(公告)日：2008-05-15
申请号：US12014501
申请日：2008-01-15
申请人： David Boerstler , Eskinder Hailu , Byron Krauter , Kazuhiko Miki , Jieming Qi
发明人： David Boerstler , Eskinder Hailu , Byron Krauter , Kazuhiko Miki , Jieming Qi
IPC分类号： H03K3/017
CPC分类号： G06F1/10 , H03K5/1565
摘要： A method, an apparatus, and a computer program are provided to measure and/or correct duty cycles. Duty cycles of various signals, specifically clocking signals, are important. However, measurement of very high frequency signals, off-chip, and in a laboratory environment can be very difficult and present numerous problems. To combat problems associated with making off-chip measurements and adjustments of signal duty cycles, comparisons are made between input signals and divided input signals that allow for easy measurement and adjustment of on-chip signals, including clocking signals.
摘要翻译： 提供了一种方法，装置和计算机程序来测量和/或校正占空比。 各种信号的占空比，特别是时钟信号是很重要的。 然而，测量非常高频率的信号，芯片外和实验室环境可能是非常困难的并且存在许多问题。 为了解决与片外测量和信号占空比调整相关的问题，可以比较输入信号和分频输入信号，从而便于测量和调整片上信号，包括时钟信号。
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公开(公告)号：US20070075370A1
公开(公告)日：2007-04-05
申请号：US11242675
申请日：2005-10-04
申请人： David Boerstler , Eskinder Hailu , Kazuhiko Miki , Jieming Qi
发明人： David Boerstler , Eskinder Hailu , Kazuhiko Miki , Jieming Qi
IPC分类号： H01L23/62
CPC分类号： G01K7/01 , G01K2217/00
摘要： The present invention provides a method, an apparatus, and a computer program product for measuring the temperature of a microprocessor through the use of ESD circuitry. The present invention uses diodes and an I/O pad within ESD circuits to determine the temperature at the location of the ESD circuitry. First, a current measuring device connects to a diode. A user or a computer program disables the protected component or circuitry, and subsequently applies a predetermined voltage to the I/O pad. This creates a reverse saturation current through the diode, which is measured by the current measuring device. From this current the user or a computer program determines the temperature of the microprocessor at the diode through the use of a graphical representation of diode reverse saturation current and corresponding temperature.
摘要翻译： 本发明提供了一种通过使用ESD电路来测量微处理器的温度的方法，装置和计算机程序产品。 本发明在ESD电路中使用二极管和I / O焊盘来确定ESD电路位置处的温度。 首先，电流测量装置连接到二极管。 用户或计算机程序禁用受保护的组件或电路，然后将预定电压施加到I / O焊盘。 这通过二极管产生反向饱和电流，由电流测量装置测量。 从该电流，用户或计算机程序通过使用二极管反向饱和电流和相应温度的图形表示来确定微处理器在二极管处的温度。
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