公开(公告)号：US07657678B2

公开(公告)日：2010-02-02

申请号：US11300131

申请日：2005-12-13

申请人： Frank W. Ahern ,  Desi Rhoden ,  Jeff Doss ,  Charles Mollo

发明人： Frank W. Ahern ,  Desi Rhoden ,  Jeff Doss ,  Charles Mollo

IPC分类号： G06F13/00

CPC分类号： G06F13/1673 ,  G06F1/1632 ,  G06F13/1642 ,  G06F13/4013 ,  G06F13/4045 ,  G06F13/4282

摘要： A modular computer system (20) including a universal connectivity station (UCS) (22) interconnected to a plurality of remote modules (30, 32, 34, 36, 38, 42) via a plurality of respective high speed serial links (26, 40) such as based on proprietary Split-Bridge™ technology. The plurality modules, including a processor module (42) which may include core parts including a CPU, memory, AGP Graphics, and system bus interface may be remotely located from each of the other modules, including the UCS (22). The present invention achieves technical advantages wherein each module of the modular computer system (20) appear to each device to be interconnected to the other on a parallel bus since the high speed serial links appear transparent. Preferably, although not necessary, each of the modules including the UCS 22 are based on the PCI bus architecture, or the PCMCIA bus architecture, although other bus architectures are well suited to be incorporated using the present invention. The processor module can be upgraded to change or improve the performance of the modular computer system 20 without requiring any changes to the remaining system, thus drastically improving the price to performance trade-offs of the system. Moreover, the operating system (OS) of each module, including both the software and hardware, do not need to be changed as the entire modular system (20) is based on a common architecture, such as the PCI or Cardbus bus architecture.

摘要翻译： 一种模块化计算机系统（20），包括通过多个相应的高速串行链路（26,26）互连到多个远程模块（30,32,34,36,38,42）的通用连接站（UCS）（22） 40），例如基于专有的Split-Bridge（TM）技术。 包括可包括CPU，存储器，AGP图形和系统总线接口的核心部分的处理器模块（42）可以远程位于包括UCS（22）的其它模块中的每一个。 本发明实现了技术优点，其中模块化计算机系统（20）的每个模块出现在每个设备上，由于高速串行链路看起来是透明的，因此在并行总线上彼此互连。 优选地，虽然不是必需的，但是包括UCS 22的每个模块都基于PCI总线架构或PCMCIA总线架构，尽管其他总线架构非常适合于使用本发明来引入。 可以升级处理器模块以改变或改进模块化计算机系统20的性能，而不需要对剩余系统进行任何改变，从而大大提高系统的价格与性能的权衡。 此外，由于整个模块化系统（20）基于诸如PCI或Cardbus总线架构的通用架构，因此不需要改变每个模块的操作系统（OS），包括软件和硬件两者。

公开(公告)号：US06782466B1

公开(公告)日：2004-08-24

申请号：US09449273

申请日：1999-11-24

申请人： James Crawford Steele ,  Desi Rhoden ,  George Crouse

发明人： James Crawford Steele ,  Desi Rhoden ,  George Crouse

IPC分类号： G06F1200

CPC分类号： G06F12/0215

摘要： A memory access approach optimizes memory address mapping for accessing data in a virtual memory arrangement wherein multiple banks of data are opened at once. One specific implementation is directed to a process of accessing data in a plurality of addressable banks of memory cells. The process involves accessing the memory cells by addressing arrays in the banks via column and row bits, and directing the address and control signals so that the addressable column address and row address bits are selected with a lower order group of the address bits directed to select the column address bits, and the next highest group of the address bits directed to select bank address bits. The next highest group of the address bits are directed to select the row address bits.

摘要翻译： 存储器访问方法优化存储器地址映射以访问虚拟存储器布置中的数据，其中多组数据立即打开。 一个具体实现涉及访问存储器单元的多个可寻址组中的数据的过程。 该过程涉及通过列和行位对存储体中的数组进行寻址来存取存储器单元，并且引导地址和控制信号，使得可寻址的列地址和行地址位被选择为指向要选择的地址位的低阶组 列地址位，以及指向选择存储区地址位的地址位的下一个最高组。 下一个最高的地址位组用于选择行地址位。

公开(公告)号：US5448264A

公开(公告)日：1995-09-05

申请号：US076826

申请日：1993-06-14

申请人： David Pinedo ,  Byron Alcorn ,  Desi Rhoden

发明人： David Pinedo ,  Byron Alcorn ,  Desi Rhoden

IPC分类号： G06T15/30 ,  G09G5/393 ,  G09G5/00

CPC分类号： G09G5/393 ,  G06T15/30

摘要： A method and apparatus for use in a computer graphics system for the storage and retrieval of pixel information is described. The computer graphics system includes a screen display. The method and apparatus are implemented in a frame buffer, wherein the frame buffer memory is divided into a first memory section for storage of the pixel information and second and third memory sections. A clipping member provides clipping information for use in the display of the pixel information in a first region of the display screen. The clipping information is stored in the second memory section. A display mode member provides display mode information for use in the display of the pixel information in a second region of the display screen. The display mode information is stored in the third memory section. The clipping information and the display information are stored in the frame buffer memory separate from one another. The frame buffer memory preferably includes an array of VRAM devices. In such an embodiment, the second memory section is contained in a first VRAM device and the third memory section is contained in a second VRAM device. The clipping information and the display mode information are stored in physically separate VRAM devices for a given pixel. The clipping information and display information are preliminarily stored in a pixel cache and transferred to the second and third sections in response to a control signal from a controller.

摘要翻译： 描述了用于计算机图形系统中用于存储和检索像素信息的方法和装置。 计算机图形系统包括屏幕显示。 该方法和装置在帧缓冲器中实现，其中帧缓冲存储器被分成用于存储像素信息的第一存储器部分和第二和第三存储器部分。 剪辑构件提供用于在显示屏幕的第一区域中的像素信息的显示中使用的剪辑信息。 剪辑信息存储在第二存储器部分中。 显示模式构件提供用于在显示屏幕的第二区域中的像素信息的显示中使用的显示模式信息。 显示模式信息存储在第三存储器部分中。 剪辑信息和显示信息被彼此分离地存储在帧缓冲存储器中。 帧缓冲存储器优选地包括VRAM设备的阵列。 在这样的实施例中，第二存储器部分被包含在第一VRAM装置中，并且第三存储器部分被包含在第二VRAM装置中。 剪辑信息和显示模式信息存储在用于给定像素的物理上分离的VRAM设备中。 剪辑信息和显示信息被预先存储在像素高速缓存中，并响应于来自控制器的控制信号传送到第二和第三部分。