公开(公告)号：US09102683B2

公开(公告)日：2015-08-11

申请号：US13598130

申请日：2012-08-29

申请人： Janis Louie ,  Puneet Kumar

发明人： Janis Louie ,  Puneet Kumar

IPC分类号： C07D487/04 ,  C07D487/10 ,  C07D491/044 ,  C07D491/04 ,  C07D313/06 ,  C07D225/04 ,  C07D491/10

CPC分类号： C07D225/04 ,  C07D313/06 ,  C07D313/20 ,  C07D487/04 ,  C07D487/10 ,  C07D491/04 ,  C07D491/048 ,  C07D491/10 ,  C07D491/107 ,  C07D491/113

摘要： Described herein are methods for synthesizing heterocyclic, 8-membered ring structures. The methods may allow for preparation of highly substituted 8-membered rings. Also disclosed are heterocyclic, 8-membered ring compounds and pharmaceutical compositions comprising the compounds.

摘要翻译： 本文描述的是合成杂环的8元环结构的方法。 该方法可以允许制备高度取代的8元环。 还公开了杂环的8元环化合物和包含该化合物的药物组合物。

公开(公告)号：US08332559B2

公开(公告)日：2012-12-11

申请号：US13413796

申请日：2012-03-07

申请人： Josh P. de Cesare ,  Ruchi Wadhawan ,  Michael J. Smith ,  Puneet Kumar ,  Bernard J. Semeria

发明人： Josh P. de Cesare ,  Ruchi Wadhawan ,  Michael J. Smith ,  Puneet Kumar ,  Bernard J. Semeria

IPC分类号： G06F13/00 ,  G06F1/32

CPC分类号： G06F1/3228 ,  G06F9/526

摘要： In an embodiment, a timer unit may be provided that may be programmed to a selected time interval, or wakeup interval. A processor may execute a wait for event instruction, and enter a low power state for the thread that includes the instruction. The timer unit may signal a timer event at the expiration of the wakeup interval, and the processor may exit the low power state in response to the timer event. The thread may continue executing with the instruction following the wait for event instruction. In an embodiment, the processor/timer unit may be used to implement a power-managed lock acquisition mechanism, in which the processor is awakened a number of times to check the lock and execute the wait for event instruction if the lock is not free, after which the thread may block until the lock is free.

摘要翻译： 在一个实施例中，可以提供可以被编程到所选择的时间间隔或唤醒间隔的定时器单元。 处理器可以执行等待事件指令，并为包括指令的线程输入低功率状态。 定时器单元可以在唤醒间隔期满时发送定时器事件，并且处理器可以响应于定时器事件而退出低功率状态。 线程可以在等待事件指令之后的指令继续执行。 在一个实施例中，处理器/定时器单元可以用于实现功率管理的锁获取机制，其中处理器被唤醒多次以检查锁定并且如果锁不是空闲的则执行等待事件指令， 之后，线程可能会阻塞，直到锁定为空。

公开(公告)号：US08316188B2

公开(公告)日：2012-11-20

申请号：US13165297

申请日：2011-06-21

申请人： Sudarshan Kadambi ,  Puneet Kumar ,  Po-Yung Chang

发明人： Sudarshan Kadambi ,  Puneet Kumar ,  Po-Yung Chang

IPC分类号： G06F12/08

CPC分类号： G06F12/0862 ,  G06F9/30047 ,  G06F9/3455 ,  G06F9/383 ,  G06F2212/6028

摘要： In one embodiment, a processor comprises a prefetch unit coupled to a data cache. The prefetch unit is configured to concurrently maintain a plurality of separate, active prefetch streams. Each prefetch stream is either software initiated via execution by the processor of a dedicated prefetch instruction or hardware initiated via detection of a data cache miss by one or more load/store memory operations. The prefetch unit is further configured to generate prefetch requests responsive to the plurality of prefetch streams to prefetch data in to the data cache. In an embodiment, the prefetch unit is configured to check for a cache hit for a prefetch request by checking a duplicate cache tags.

摘要翻译： 在一个实施例中，处理器包括耦合到数据高速缓存的预取单元。 预取单元被配置为同时维护多个单独的活动预取流。 每个预取流是由处理器执行专用预取指令的软件或通过一个或多个加载/存储存储器操作通过检测到数据高速缓存未命中而启动的硬件。 预取单元还被配置为响应于多个预取流来生成预取请求，以将数据预取到数据高速缓存中。 在一个实施例中，预取单元被配置为通过检查重复的高速缓存标签来检查预取请求的高速缓存命中。

公开(公告)号：US08156275B2

公开(公告)日：2012-04-10

申请号：US12465182

申请日：2009-05-13

申请人： Josh P. de Cesare ,  Ruchi Wadhawan ,  Michael J. Smith ,  Puneet Kumar ,  Bernard J. Semeria

发明人： Josh P. de Cesare ,  Ruchi Wadhawan ,  Michael J. Smith ,  Puneet Kumar ,  Bernard J. Semeria

IPC分类号： G06F13/00 ,  G06F1/32

CPC分类号： G06F1/3228 ,  G06F9/526

摘要： In an embodiment, a timer unit may be provided that may be programmed to a selected time interval, or wakeup interval. A processor may execute a wait for event instruction, and enter a low power state for the thread that includes the instruction. The timer unit may signal a timer event at the expiration of the wakeup interval, and the processor may exit the low power state in response to the timer event. The thread may continue executing with the instruction following the wait for event instruction. In an embodiment, the processor/timer unit may be used to implement a power-managed lock acquisition mechanism, in which the processor is awakened a number of times to check the lock and execute the wait for event instruction if the lock is not free, after which the thread may block until the lock is free.

公开(公告)号：US20100293401A1

公开(公告)日：2010-11-18

申请号：US12465182

申请日：2009-05-13

申请人： Josh P. de Cesare ,  Ruchi Wadhawan ,  Michael J. Smith ,  Puneet Kumar ,  Bernard J. Semeria

发明人： Josh P. de Cesare ,  Ruchi Wadhawan ,  Michael J. Smith ,  Puneet Kumar ,  Bernard J. Semeria

IPC分类号： G06F1/32

CPC分类号： G06F1/3228 ,  G06F9/526

摘要： In an embodiment, a timer unit may be provided that may be programmed to a selected time interval, or wakeup interval. A processor may execute a wait for event instruction, and enter a low power state for the thread that includes the instruction. The timer unit may signal a timer event at the expiration of the wakeup interval, and the processor may exit the low power state in response to the timer event. The thread may continue executing with the instruction following the wait for event instruction. In an embodiment, the processor/timer unit may be used to implement a power-managed lock acquisition mechanism, in which the processor is awakened a number of times to check the lock and execute the wait for event instruction if the lock is not free, after which the thread may block until the lock is free.

摘要翻译： 在一个实施例中，可以提供可以被编程到所选择的时间间隔或唤醒间隔的定时器单元。 处理器可以执行等待事件指令，并为包括指令的线程输入低功率状态。 定时器单元可以在唤醒间隔期满时发送定时器事件，并且处理器可以响应于定时器事件而退出低功率状态。 线程可以在等待事件指令之后的指令继续执行。 在一个实施例中，处理器/定时器单元可以用于实现功率管理的锁获取机制，其中处理器被唤醒多次以检查锁定并且如果锁不是空闲的则执行等待事件指令， 之后，线程可能会阻塞，直到锁定为空。

公开(公告)号：US6073135A

公开(公告)日：2000-06-06

申请号：US37350

申请日：1998-03-10

申请人： Andrei Z. Broder ,  Michael Burrows ,  Monika H. Henzinger ,  Sanjay Ghemawat ,  Puneet Kumar ,  Suresh Venkatasubramanian

发明人： Andrei Z. Broder ,  Michael Burrows ,  Monika H. Henzinger ,  Sanjay Ghemawat ,  Puneet Kumar ,  Suresh Venkatasubramanian

IPC分类号： G06F17/30

CPC分类号： G06F17/30882 ,  G06F17/30873 ,  Y10S707/99932 ,  Y10S707/99933 ,  Y10S707/99937

摘要： A server computer is provided for representing and navigating the connectivity of Web pages. The Web pages include links to other Web pages. The links and Web page s have associated names (URLs). The names of the Web pages are sorted in a memory of the connectivity server. The sorted names are delta encoded while periodically storing full names as checkpoints in the memory. Each delta encoded name and checkpoint has a unique identification. A list of pairs of identifications representing existent links is sorted twice, first according to the first identification of each pair to produce an inlist, and second according to the second identification of each pair to produce an outlist. An array of elements is stored in the memory, there is one array element for each Web page. Each element includes a first pointer to one of the checkpoints, a second pointer to an associated inlist of the Web page, and a third pointer to an associated outlist of the Web page. The array is indexed by a particular identification to locate connected Web pages.

摘要翻译： 提供服务器计算机用于表示和浏览网页的连接。 网页包含指向其他网页的链接。 链接和网页都有相关联的名称（URL）。 网页的名称在连接服务器的内存中排序。 排序的名称是增量编码的，同时周期性地将全名作为检查点存储在内存中。 每个delta编码的名称和检查点都有唯一的标识。 代表存在的链接的标识对的列表被分类两次，首先根据每对的第一个标识来产生一个列表，其次是根据每一对的第二个标识来产生一个列表。 元素数组存储在内存中，每个网页有一个数组元素。 每个元素包括指向其中一个检查点的第一指针，指向该网页的相关联列表的第二指针，以及指向该网页的相关联的列表的第三指针。 该阵列由特定的标识索引，以定位连接的网页。