利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

38 条记录 (耗时 0.023 秒)

    System and method for data transfer across multiple clock domains
    21.
    发明授权
    System and method for data transfer across multiple clock domains 失效
    跨多个时钟域进行数据传输的系统和方法

    公开(公告)号：US6163545A

    公开(公告)日：2000-12-19

    申请号：US7802

    申请日：1998-01-15

    申请人： Paul Flood ,  Eugene O'Neill

    发明人： Paul Flood ,  Eugene O'Neill

    IPC分类号： H04L7/02 ,  H04L25/05 ,  H04J3/16

    CPC分类号： H04L7/02 ,  H04L25/05

    摘要： A system for converting data in one clock domain to a second clock domain comprises a multiplexer which has a select control which is synchronous with a first frequency and is coupled to two bistable registers of which a first is clock controlled in accordance with the first frequency and a second is clock controlled by the second frequency. The data output of the first register is looped back to the second data input of the multiplexer. The select signal operates to couple a data input to the first register whereupon the multiplexer then serves to couple the data output of the first register back to the data input thereof. The arrangement ensures availability of data at the first clock frequency beyond a transition of the second clock frequency. Thus data, preferably multi-bit address data, can be transferred from one clock domain to another with less delay than in customary systems.

    摘要翻译： 用于将一个时钟域中的数据转换为第二时钟域的系统包括多路复用器，其具有与第一频率同步的选择控制，并且耦合到两个双稳态寄存器，其中第一个是根据第一频率进行时钟控制的; 第二个是由第二个频率控制的时钟。 第一个寄存器的数据输出环回到多路复用器的第二个数据输入端。 选择信号用于将数据输入耦合到第一寄存器，于是多路复用器然后用于将第一寄存器的数据输出耦合回其数据输入。 该布置确保在第二时钟频率的转变之后的第一时钟频率的数据的可用性。 因此，数据，优选多位地址数据可以从一个时钟域传输到另一个时钟域，而不是传统系统中的延迟。

    Direct data placement and message reassembly
    23.
    发明授权
    Direct data placement and message reassembly 失效
    直接数据放置和消息重新组装

    公开(公告)号：US06779056B2

    公开(公告)日：2004-08-17

    申请号：US09897044

    申请日：2001-07-03

    申请人： Eugene O'Neill ,  Richard A Gahan

    发明人： Eugene O'Neill ,  Richard A Gahan

    IPC分类号： G06F300

    CPC分类号： H04L49/9094 ,  H04L49/90 ,  H04L49/9063 ,  H04L69/12 ,  H04L69/16 ,  H04L69/161 ,  H04L69/163

    摘要： A direct data placement implementation for a data reassembly process. Data within a protocol data unit is placed directly in preassigned application buffers. The network interface card has buffer space into which message headers, segment headers and indicators of escaped data and size of escaped data are placed. A single buffer can contain this information for a complete PDU (or message) and is handed over to enable the next process to run on a per message basis.

    摘要翻译： 数据重组过程的直接数据放置实现。 协议数据单元中的数据直接放置在预先分配的应用程序缓冲区中。 网络接口卡具有缓冲空间，消息头，段头和转义数据的指示符以及转义数据的大小被放置到其中。 单个缓冲区可以包含用于完整PDU（或消息）的该信息，并且被移交以使下一个进程能够在每个消息的基础上运行。

    Integrated data table in a network
    25.
    发明授权
    Integrated data table in a network 有权
    网络中集成数据表

    公开(公告)号：US06661787B1

    公开(公告)日：2003-12-09

    申请号：US09286470

    申请日：1999-04-06

    申请人： Anne G. O'Connell ,  Eugene O'Neill ,  Una Quinlan

    发明人： Anne G. O'Connell ,  Eugene O'Neill ,  Una Quinlan

    IPC分类号： H04L1256

    CPC分类号： H04L45/742 ,  H04L12/4625 ,  H04L12/4641

    摘要： A method of operating a network device in a communication system for the transmission of data packets which include network addresses identifying sources and destinations of data, the network device being capable of both bridging and routing decisions and including a forwarding database by means of which a packet including network address data can be forwarded to at least one port and thereby to at least one network path identified by a network address, and packets can be forwarded to at least one port in response to a media access control address. The method comprises establishing a data table which contains entries comprising a network address of an end station to which a packet is destined, a respective media access control address and an identification of at least one port to which the packet will be directed within the device. The table is accessed in response to network addresses and media access control addresses, whereby the same table can be used for both routing and bridging decisions.

    摘要翻译： 一种在用于传输数据分组的通信系统中操作网络设备的方法，所述数据分组包括识别数据的源和目的地的网络地址，所述网络设备能够进行桥接和路由决策，并且包括转发数据库，​​通过该转发数据库， 包括网络地址数据可以转发到至少一个端口，从而被转发到由网络地址标识的至少一个网络路径，并且可以响应于媒体访问控制地址将数据包转发到至少一个端口。 该方法包括建立数据表，该数据表包含包含分组所去往的终端站的网络地址的条目，相应的媒体访问控制地址以及分组将在该设备内被引导到的至少一个端口的标识。 响应于网络地址和媒体访问控制地址访问该表，由此同一表可以用于路由和桥接决定。

    Lump process alpha gypsum
    26.
    发明授权
    Lump process alpha gypsum 失效
    块法阿尔法石膏

    公开(公告)号：US4309391A

    公开(公告)日：1982-01-05

    申请号：US212464

    申请日：1980-12-03

    申请人： Eugene O'Neill

    发明人： Eugene O'Neill

    IPC分类号： C04B11/032 ,  C04B11/02 ,  C01F11/46

    CPC分类号： C04B11/032

    摘要： An improved "lump" process for producing alpha gypsum, calcium sulfate hemihydrate, from natural gypsum rock of the type wherein lumps of gypsum rock particles (a minimum of about 1/2 inch or 1.3 cm. in size) are calcined to low water-demand alpha hemihydrate by autoclaving in a saturated steam atmosphere, quickly dried and pulverized is disclosed. The improvement allows the thorough processing of natural gypsum as large sized particles or containing considerable selenite and includes the steps of initiating calcination without crystal habit modifier and, after hemihydrate formation has commenced, adding crystal habit modifier and completing calcination under increased steam pressure.

    摘要翻译： 从石膏岩石颗粒（最小约1/2英寸或1.3厘米的尺寸）的块状煅烧成低水溶性的天然石膏岩，生产α-石膏，半水硫酸钙的改进的“块”方法， 公开了在饱和蒸汽气氛中通过高压灭菌来要求α半水合物，快速干燥和粉碎。 该改进允许天然石膏作为大尺寸颗粒或含有相当大的亚硒酸盐的彻底处理，并且包括在没有晶体习性调节剂的情况下开始煅烧的步骤，并且在半水合物形成开始后，添加水晶习性调节剂并在增加的蒸汽压力下完成煅烧。

    POSITIONALLY DEPENDENT PATTERN CHECKING IN CHARACTER STRINGS USING DETERMINISTIC FINITE AUTOMATA
    27.
    发明申请
    POSITIONALLY DEPENDENT PATTERN CHECKING IN CHARACTER STRINGS USING DETERMINISTIC FINITE AUTOMATA 有权
    使用确定性有限自动机器的字符串中的垂直相关图案检查

    公开(公告)号：US20120084245A1

    公开(公告)日：2012-04-05

    申请号：US13252776

    申请日：2011-10-04

    申请人： David Law ,  Peter Furlong ,  Eugene O'Neill ,  Kevin Loughran

    发明人： David Law ,  Peter Furlong ,  Eugene O'Neill ,  Kevin Loughran

    IPC分类号： G06N5/02

    CPC分类号： H04L45/742 ,  H04L69/22

    摘要： An apparatus including logic to receive a data packet comprising a string of characters, said apparatus having a plurality of states and at least one state for every character position in the string of characters; logic to examine the string of characters for matches with a plurality of predefined values, beginning with an initial character; and logic to execute forward exit transitions from any of the plurality of states based upon the examination of the characters, wherein a current state of the apparatus represents a count of a number of characters from the initial character of the string of characters.

    摘要翻译： 一种装置，包括用于接收包括一串字符的数据分组的逻辑，所述装置具有多个状态，并且至少一个状态用于字符串中的每个字符位置; 检查用于与初始字符开始的多个预定义值匹配的字符串的逻辑; 以及基于对所述字符的检查来执行从所述多个状态中的任何一个状态的向前退出转换的逻辑，其中所述装置的当前状态表示从所述字符串的初始字符开始的字符数的计数。

    Positionally dependent pattern checking in character strings using deterministic finite automata
    28.
    发明授权
    Positionally dependent pattern checking in character strings using deterministic finite automata 有权
    使用确定性有限自动机的字符串中的位置依赖模式检查

    公开(公告)号：US08060546B2

    公开(公告)日：2011-11-15

    申请号：US11848302

    申请日：2007-08-31

    申请人： David Law ,  Peter Furlong ,  Eugene O'Neill ,  Kevin Loughran

    发明人： David Law ,  Peter Furlong ,  Eugene O'Neill ,  Kevin Loughran

    IPC分类号： G06F7/00

    CPC分类号： H04L45/742 ,  H04L69/22

    摘要： A deterministic finite state machine organised for the detection of positionally significant matches of characters in a string of characters examines each character in turn to determine a exit transition for a current state of the machine to another state The machine responds to an examination of the string of characters by executing in response to a first character at the commencement of the string a transition from an initial state to another state. The machine has at least one state for every character position, includes a exit transition from each state for each character to another state; and possesses only forward exit transitions each from any of the states whereby the current state of the machine unambiguously represents a count of the number of characters from the commencement of the string. The machine may include at least one match state which indicates that all character matches in the string required by at least one respective rule have been detected. Some but not all the states in the multiplicity of states each have a single exit transition for any value of a respective character in the string. At least some of the states in the multiplicity of states each define an exit transition to a state indicating ‘no match’. The machine may be disposed to cease its examination of the character string on attaining a ‘no match’state.

    摘要翻译： 组织为用于检测字符串中的字符的位置有意义的匹配的确定性有限状态机依次检查每个字符以确定机器的当前状态到另一状态的退出转换。机器响应于对字符串的检查 通过在字符串开始时响应于第一个字符执行从初始状态到另一状态的转变的字符。 机器对于每个字符位置至少有一个状态，包括从每个字符到另一个状态的每个状态的退出转换; 并且仅具有从任何状态的前向退出转换，由此机器的当前状态明确地表示从字符串的开始处的字符数的计数。 机器可以包括至少一个匹配状态，其指示已经检测到至少一个相应规则所需的字符串中的所有字符匹配。 多个状态中的一些但不是全部状态各自对于字符串中相应字符的任何值都具有单个退出转换。 多个状态中的至少一些状态各自定义到指示“不匹配”的状态的退出转换。 可以处理机器以在获得“不匹配”状态时停止对字符串的检查。

    Programmable FIFO memory scheme
    29.
    发明授权
    Programmable FIFO memory scheme 有权
    可编程FIFO存储器方案

    公开(公告)号：US06233651B1

    公开(公告)日：2001-05-15

    申请号：US08981140

    申请日：1999-01-20

    申请人： Eugene O'Neill ,  Anne O'Connell

    发明人： Eugene O'Neill ,  Anne O'Connell

    IPC分类号： G06F1200

    CPC分类号： G06F5/065

    摘要： A large FIFO memory device has its total available memory capacity partitioned into memory sections. The partitions are in the form of programmable delimiters in order to determine flexibly the size of the memory sections.

    摘要翻译： 一个大的FIFO存储器设备的总可用内存容量分为存储器部分。 这些分区是可编程分隔符的形式，以便灵活地确定存储器部分的大小。