利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

7 条记录 (耗时 0.011 秒)

    On-chip detection of clock gitches by examination of consecutive data
    3.
    发明授权
    On-chip detection of clock gitches by examination of consecutive data 失效
    通过检查连续数据片上检测时钟接头

    公开(公告)号：US06543027B1

    公开(公告)日：2003-04-01

    申请号：US09671121

    申请日：2000-09-28

    申请人： Mark A Hughes ,  Joseph N Butler ,  Neil O Fanning

    发明人： Mark A Hughes ,  Joseph N Butler ,  Neil O Fanning

    IPC分类号： G06F1100

    CPC分类号： G11C7/1018 ,  G11C7/1072 ,  G11C29/14

    摘要： An application specific integrated circuit includes a clock recovery circuit which recovers from an input signal a repetitive sequence of data values wherein no two consecutive values are the same and a recovered clock. An address generator responds to the recovered clock to cause storage of the data values in said memory in a set of locations having addresses generated by the address generator, so that the address generated by the generator increments in response to a repetitive transition in the recovered clock. The existence of a clock glitch is found by reading the data values from the set of locations to determine whether any two consecutive locations contain the same data value.

    摘要翻译： 专用集成电路包括时钟恢复电路，其从输入信号中恢复其中没有两个连续值相同的数据值的重复序列和恢复的时钟。 地址发生器响应于恢复的时钟，以使得存储器中的数据值存储在具有由地址发生器产生的地址的一组位置中，使得由发生器产生的地址响应于恢复的时钟中的重复转换而递增 。 通过读取位置集合中的数据值来确定是否有任何两个连续的位置包含相同的数据值来发现存在时钟毛刺。

    High speed parallel bit error rate tester
    4.
    发明授权
    High speed parallel bit error rate tester 失效
    高速并行位错误率测试仪

    公开(公告)号：US06438717B1

    公开(公告)日：2002-08-20

    申请号：US09436350

    申请日：1999-11-09

    申请人： Joseph N Butler ,  Mark A Hughes ,  Neil O Fanning ,  Eugene O'Neill ,  Una Quinlan

    发明人： Joseph N Butler ,  Mark A Hughes ,  Neil O Fanning ,  Eugene O'Neill ,  Una Quinlan

    IPC分类号： G06F1100

    CPC分类号： H04L1/20 ,  H04L1/0001 ,  H04L25/14

    摘要： A high speed link between chips and comprising a multiplicity of synchronous serial data channels includes an onboard detector for detecting an error rate for each channel. The transmitter and the receiver chips are configured in response to the detector to select the channel having the lowest error rate as the control channel and optionally to render at least the channel with the highest error rate inactive.

    摘要翻译： 芯片之间的高速链路包括多个同步串行数据信道，包括用于检测每个信道的错误率的板上检测器。 响应于检测器配置发射机和接收机芯片，以选择具有最低误码率的信道作为控制信道，并且可选地使至少具有最高错误率的信道无效。

    Framing codes for high-speed parallel data buses
    5.
    发明授权
    Framing codes for high-speed parallel data buses 失效
    高速并行数据总线的成帧代码

    公开(公告)号：US06275880B1

    公开(公告)日：2001-08-14

    申请号：US09253537

    申请日：1999-02-22

    申请人： Una Quinlan ,  Con Cremin ,  Eugene O'Neill ,  J. Noel Butler ,  Mark A. Hughes ,  Neil O. Fanning

    发明人： Una Quinlan ,  Con Cremin ,  Eugene O'Neill ,  J. Noel Butler ,  Mark A. Hughes ,  Neil O. Fanning

    IPC分类号： G06F1300

    CPC分类号： H04L1/0063 ,  H04L1/0072 ,  Y10S707/99942 ,  Y10S707/99943 ,  Y10S707/99944

    摘要： A plurality of serial data streams are transmitted on a corresponding plurality of lines at a common frequency in equal groups of symbols. A framing signal composed of groups of symbols corresponding in number to groups of data symbols is transmitted on an additional control line. Each group of symbols in the framing signal includes a majority of symbols capable of representing a first plurality of code words and a second plurality, substantially less than the first plurality, of valid code words, and a minority of symbols which constitute parity check symbols. Each of the valid code words consists of a first sub-group of similar symbols and a second plurality of similar symbols. For some of the valid code words the symbols in the first sub-group are similar to the symbols in the second sub-group. For other valid code words the symbols in the first sub-group are different from the symbols in the second sub-group. The valid code words correspond to groups which represent (a) start of a data packet or block; (b) data/(c) a gap between groups of data; and (d) an idle state. The sequence of groups in the framing signal is monitored by means of a state machine.

    摘要翻译： 多个串行数据流以相等的符号组以公共频率在对应的多条线上发送。 在附加控制线上发送由多个数据符号组对应的符号组构成的成帧信号。 成帧信号中的每组符号包括能够表示第一多个码字的多数符号，以及基本上小于第一多个有效码字的第二多个符号，以及构成奇偶校验符号的少数符号。 每个有效代码字由相似符号的第一子组和第二多个相似符号组成。 对于一些有效的代码字，第一子组中的符号与第二子组中的符号相似。 对于其他有效的代码字，第一子组中的符号与第二子组中的符号不​​同。 有效码字对应于表示（a）数据包或块的开始的组; （b）数据/（c）数据组之间的差距; 和（d）空闲状态。 通过状态机监视成帧信号中的组的序列。