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公开(公告)号：US08860722B2
公开(公告)日：2014-10-14
申请号：US12002732
申请日：2007-12-17
CPC分类号： G06T15/005 , G06T1/20 , G06T15/405
摘要： Early Z scoreboard tracking systems and methods in accordance with the present invention are described. Multiple pixels are received and a pixel depth raster operation is performed on the pixels. The pixel depth raster operation comprises discarding a pixel that is occluded. In one exemplary implementation, the depth raster operation is done at a faster rate than a color raster operation. Pixels that pass the depth raster operation are checked for screen coincidence. Pixels with screen coincidence are stalled and pixels without screen coincidence are forwarded to lower stages of the pipeline. The lower stages of the pipeline are programmable and pixel flight time can vary (e.g., can include multiple passes through the lower stages). Execution through the lower stages is directed by a program sequencer which also directs notification to the pixel flight tracking when a pixel is done processing.
摘要翻译： 描述根据本发明的早期Z记分板跟踪系统和方法。 接收多个像素，并对像素执行像素深度光栅操作。 像素深度光栅操作包括丢弃被遮挡的像素。 在一个示例性实现中，深度光栅操作以比彩色光栅操作更快的速度完成。 检查通过深度光栅操作的像素的屏幕重合。 具有屏幕巧合的像素停止，而没有屏幕一致的像素被转发到流水线的较低阶段。 管道的较低级是可编程的，并且像素飞行时间可以变化（例如，可以包括通过下级的多次）。 较低阶段的执行由程序定序器执行，程序定序器还在像素完成处理时指示像素飞行跟踪。
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22.发明授权Method and system for implementing multiple high precision and low precision interpolators for a graphics pipeline 有权用于为图形管线实现多个高精度和低精度内插器的方法和系统公开(公告)号：US08749576B2
公开(公告)日：2014-06-10
申请号：US11482669
申请日：2006-07-06
IPC分类号： G09G5/00
CPC分类号： G06T15/005 , G06T11/40
摘要： A rasterizer stage configured to implement multiple interpolators for graphics pipeline. The rasterizer stage includes a plurality of simultaneously operable low precision interpolators for computing a first set of pixel parameters for pixels of a geometric primitive and a plurality of simultaneously operable high precision interpolators for computing a second set of pixel parameters for pixels of the geometric primitive. The rasterizer stage also includes an output mechanism coupled to the interpolators for routing computed pixel parameters into a memory array. Parameters may be programmably assigned to the interpolators and the results thereof may be programmably assigned to portions of a pixel packet.
摘要翻译： 光栅化器级配置为实现图形管线的多个插值器。 光栅化器级包括多个可同时操作的低精度内插器，用于计算几何图元的像素的第一组像素参数和用于计算几何图元的像素的第二组像素参数的多个可同时操作的高精度内插器。 光栅化器级还包括耦合到内插器的输出机构，用于将计算出的像素参数路由到存储器阵列中。 参数可以可编程地分配给内插器，并且其结果可以可编程地分配给像素分组的部分。
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公开(公告)号：US08736620B2
公开(公告)日：2014-05-27
申请号：US10846201
申请日：2004-05-14
CPC分类号： G06T15/005
摘要： A present invention pixel processing system and method permit complicated three dimensional images to be rendered with shallow graphics pipelines including reduced gate counts and also facilitates power conservation. Pixel packet information includes pixel surface attribute values are retrieved in a single unified data fetch stage. At a data fetch pipestage a determination may be made if the pixel packet information contributes to an image display presentation (e.g., a depth comparison of Z values is performed determine if the pixel is occluded). A pixel packet status indicator (e.g., a kill bit) is set in the sideband portion of a pixel packet and the pixel packet is forwarded for processing in accordance with the pixel packet status indicator. The status indicator is a kill bit is set to prevent logic components from clocking information for a payload portion of the pixel packet if the status indicator indicates the pixel packet payload does not contribute to the image display presentation while continuing to clock pixel packet sideband information.
摘要翻译： 本发明的像素处理系统和方法允许使用包括减少的栅极数量的浅图形管线来呈现复杂的三维图像，并且还有助于功率节省。 像素分组信息包括像素表面属性值在单个统一数据获取阶段检索。 在数据提取管线处，可以确定像素分组信息是否有助于图像显示呈现（例如，执行Z值的深度比较来确定像素是否被遮挡）。 像素分组状态指示符（例如，杀死比特）被设置在像素分组的边带部分中，并且像素分组被转发以根据像素分组状态指示符进行处理。 如果状态指示符指示像素分组有效载荷对图像显示呈现不起作用，同时继续对像素分组边带信息进行时钟处理，则状态指示符是设置为防止逻辑组件针对像素分组的有效载荷部分的时钟信息。
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公开(公告)号：US08711155B2
公开(公告)日：2014-04-29
申请号：US10845662
申请日：2004-05-14
CPC分类号： G06T15/40 , G06F9/3867 , G06F9/3869 , G06T15/005 , G06T2200/28
摘要： A pixel processing system and method which permits rendering of complicated three dimensional images using a shallow graphics pipeline including reduced gate counts and low power operation. Pixel packet information includes pixel surface attribute values retrieved in a single unified data fetch stage. A determination is made if the pixel packet information contributes to an image display presentation (e.g., a depth comparison of Z values may be performed). The pixel packet information processing is handled in accordance with results of the determining. The pixel surface attribute values and pixel packet information are removed from further processing if the pixel surface attribute values are occluded. In one exemplary implementation, the pixel packet includes a plurality of rows and the handling is coordinated for the plurality of rows. Any of a number of downstream pipestages may remove the occluded pixel information, and in response thereto, may notify a gatekeeper pipestage of the slack increase so that more pixels can be allowed into the pipeline.
摘要翻译： 一种像素处理系统和方法，其允许使用包括减少的门数和低功率操作的浅图形管线来呈现复杂的三维图像。 像素分组信息包括在单个统一数据获取阶段检索的像素表面属性值。 如果像素分组信息有助于图像显示呈现（例如，可以执行Z值的深度比较），则确定。 根据确定的结果处理像素分组信息处理。 如果像素表面属性值被遮挡，则像素表面属性值和像素分组信息从进一步处理中去除。 在一个示例性实现中，像素分组包括多个行，并且对于多个行来协调处理。 多个下游管道中的任何一个可以去除遮挡的像素信息，并且响应于此，可以通知网守管道的松弛增加，使得可以允许更多的像素进入流水线。
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25.发明授权Method and system for implementing clamped z value interpolation in a raster stage of a graphics pipeline 有权用于在图形管线的光栅阶段中实现钳位的z值插值的方法和系统公开(公告)号：US08432394B1
公开(公告)日：2013-04-30
申请号：US10845992
申请日：2004-05-14
申请人： Edward A. Hutchins
发明人： Edward A. Hutchins
IPC分类号： G06T15/40
CPC分类号： G06T15/405
摘要： A method of computing z parameters for pixels of a geometric primitive. The method includes the step of accessing the geometric primitive comprising a plurality of vertices, wherein each vertex comprises a plurality of associated parameters including a depth parameter, z. During rasterization of the geometric primitive, respective z values are interpolated for each pixel of the geometric primitive. Each z value is represented within a predefined numerical range which substantially corresponds to a depth range between a near plane and a far plane related to pixel rendering. During the interpolating, the z values are allowed to exceed the predefined numerical range and roll over within the predefined numerical range. A multi-bit indicator is used to indicate when a z value for a pixel is outside of the depth range.
摘要翻译： 一种计算几何图元像素的z参数的方法。 该方法包括访问包括多个顶点的几何图元的步骤，其中每个顶点包括多个相关参数，包括深度参数z。 在几何图元的光栅化期间，对于几何图元的每个像素插入相应的z值。 每个z值被表示在预定的数值范围内，其基本上对应于与像素渲染相关的近平面和远平面之间的深度范围。 在内插期间，允许z值超过预定义的数值范围，并在预定义的数值范围内翻转。 多位指示器用于指示像素的z值何时超出深度范围。
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26.发明授权公开(公告)号：US08416242B1
公开(公告)日：2013-04-09
申请号：US10846786
申请日：2004-05-14
申请人： Edward A. Hutchins
发明人： Edward A. Hutchins
IPC分类号： G06T17/00
CPC分类号： G06T15/00 , G06T11/40 , G06T2210/36
摘要： A method determining LOD values for a geometric primitive, in accordance with one embodiment of the present invention, includes accessing a plurality of geometric parameters of a vertex. An LOD value for a vertex is calculated as a function of the plurality of parameters of the vertex in a setup module. In a raster module an LOD value for a pixel is interpolated as a function of the LOD value of the pixel corresponding to the vertex and a view distance of the non-vertex pixel.
摘要翻译： 根据本发明的一个实施例，确定几何图元的LOD值的方法包括访问顶点的多个几何参数。 根据设置模块中的顶点的多个参数计算顶点的LOD值。 在光栅模块中，将像素的LOD值作为与顶点对应的像素的LOD值和非顶点像素的视距进行插值。
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公开(公告)号：US08411096B1
公开(公告)日：2013-04-02
申请号：US11893503
申请日：2007-08-15
CPC分类号： G06T15/005 , G06F9/3881
摘要： Embodiments for programming a graphics pipeline, and modules within the graphics pipeline, are detailed herein. Several of these embodiments utilize offset registers associated with the instruction tables for the modules within the pipeline. The offset register serves as a pointer to locations in the instruction table, which allows instructions to be written to be instruction table, without requiring that the shader programs have explicit addresses. One embodiment describes a method of programming a graphics pipeline. This method involves accessing the shader program stored in memory. A shader instruction is generated from this shader program, and loaded into an instruction table associated with a target module graphics pipeline. The shader instruction is loaded into the instruction table at the location indicated by an offset register.
摘要翻译： 本文详细描述了用于编程图形管线和图形流水线内的模块的实施例。 这些实施例中的几个使用与管线内的模块的指令表相关联的偏移寄存器。 偏移寄存器用作指向指令表中的位置的指针，其允许将指令写入指令表，而不要求着色器程序具有显式地址。 一个实施例描述了编程图形流水线的方法。 该方法涉及访问存储在内存中的着色程序。 着色器指令从该着色器程序生成，并加载到与目标模块图形管道相关联的指令表中。 着色器指令在偏移寄存器指示的位置加载到指令表中。
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28.发明授权System and method for a universal data write unit in a 3-D graphics pipeline including generic cache memories 有权用于包含通用高速缓存存储器的3-D图形管线中的通用数据写入单元的系统和方法公开(公告)号：US07724263B2
公开(公告)日：2010-05-25
申请号：US10846774
申请日：2004-05-14
申请人： Edward A. Hutchins , Paul Kim , Brian K. Angell
发明人： Edward A. Hutchins , Paul Kim , Brian K. Angell
CPC分类号： G06F12/0875 , G06T1/60 , G06T15/005
摘要： A system and method for a data write unit in a 3-D graphics pipeline including generic cache memories. Specifically, in one embodiment a data write unit includes a first memory, a plurality of cache memories and a data write circuit. The first memory receives a pixel packet associated with a pixel. The pixel packet includes data related to surface characteristics of the pixel. The plurality of cache memories is coupled to the first memory for storing pixel information associated with a plurality of surface characteristics of a plurality of pixels. Each of the plurality of cache memories is programmably associated with a designated surface characteristic. The data write circuit is coupled to the first a memory and the plurality of cache memories. The data write circuit is operable under program control to obtain designated portions of the pixel packet for storage into the plurality of cache memories.
摘要翻译： 一种用于包含通用高速缓冲存储器的3-D图形管线中的数据写入单元的系统和方法。 具体地，在一个实施例中，数据写入单元包括第一存储器，多个高速缓冲存储器和数据写入电路。 第一存储器接收与像素相关联的像素分组。 像素分组包括与像素的表面特性有关的数据。 多个高速缓冲存储器耦合到第一存储器，用于存储与多个像素的多个表面特性相关联的像素信息。 多个高速缓冲存储器中的每一个可编程地与指定的表面特性相关联。 数据写入电路耦合到第一个存储器和多个高速缓存存储器。 数据写入电路在程序控制下可操作以获得用于存储到多个高速缓冲存储器中的像素分组的指定部分。
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公开(公告)号：US08698819B1
公开(公告)日：2014-04-15
申请号：US11893439
申请日：2007-08-15
CPC分类号： G06T1/20
摘要： Embodiments for programming a graphics pipeline, and modules within the graphics pipeline, are detailed herein. One embodiment described a method of implementing software assisted shader merging for a graphics pipeline. The method involves accessing a first shader program in memory, and generating a first shader instruction from that program. This first instruction is loaded into an instruction table at a first location, indicated by an offset register. A second shader program in memory is then accessed, and used to generate a second shader instruction. The second shader instruction is loaded into the instruction table at a second location indicated by the offset register.
摘要翻译： 本文详细描述了用于编程图形管线和图形流水线内的模块的实施例。 一个实施例描述了为图形管线实现软件辅助着色器合并的方法。 该方法涉及访问存储器中的第一着色器程序，并从该程序生成第一着色器指令。 该第一指令被加载到由偏移寄存器指示的第一位置的指令表中。 然后访问存储器中的第二个着色器程序，并用于生成第二个着色器指令。 第二个着色器指令在由偏移寄存器指示的第二个位置加载到指令表中。
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30.发明授权Program sequencer for generating indeterminant length shader programs for a graphics processor 有权用于为图形处理器生成不确定长度着色器程序的程序定序器公开(公告)号：US08659601B1
公开(公告)日：2014-02-25
申请号：US11893404
申请日：2007-08-15
CPC分类号： G06T15/005 , G06F9/5083 , G06T1/20
摘要： A method for loading and executing an indeterminate length shader program. The method includes accessing a first portion of a shader program in graphics memory of a GPU and loading instructions from the first portion into a plurality of stages of the GPU to configure the GPU for program execution. A group of pixels is then processed in accordance with the instructions from the first portion. A second portion of the shader program is accessed in graphics memory of the GPU and instructions from the second portion are loaded into the plurality of stages of the GPU to configure the GPU for program execution. The group of pixels are then processed in accordance with the instructions from the second portion.
摘要翻译： 一种用于加载和执行不确定长度着色器程序的方法。 该方法包括访问GPU的图形存储器中的着色器程序的第一部分，并且将指令从第一部分加载到GPU的多个阶段以配置GPU用于程序执行。 然后根据来自第一部分的指令对一组像素进行处理。 在GPU的图形存储器中访问着色器程序的第二部分，并且来自第二部分的指令被加载到GPU的多个级中以配置GPU用于程序执行。 然后根据来自第二部分的指令对像素组进行处理。
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