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    METHOD OF LAYING OUT INTEGRATED CIRCUIT DESIGN BASED ON KNOWN POLYSILICON PERIMETER DENSITIES OF INDIVIDUAL CELLS
    21.
    发明申请
    METHOD OF LAYING OUT INTEGRATED CIRCUIT DESIGN BASED ON KNOWN POLYSILICON PERIMETER DENSITIES OF INDIVIDUAL CELLS 有权
    基于个体电池的已知多晶硅密度的集成电路设计方法

    公开(公告)号：US20090282380A1

    公开(公告)日：2009-11-12

    申请号：US12117761

    申请日：2008-05-09

    申请人： Laura S. Chadwick ,  James A. Culp ,  David J. Hathaway ,  Anthony D. Polson

    发明人： Laura S. Chadwick ,  James A. Culp ,  David J. Hathaway ,  Anthony D. Polson

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5068

    摘要： Disclosed is a method of laying out individual cells of an integrated circuit design, based at least in part on the known polysilicon perimeter densities of those cells. That is, the method embodiments use the knowledge of polysilicon perimeter density for known cells to drive placement of those cells on a chip (i.e., to drive floor-planning). The method embodiments can be used to achieve approximately uniform across-chip polysilicon perimeter density and, thereby to limit performance parameter variations between functional devices that are attributable to variations in polysilicon perimeter density. Alternatively, the method embodiments can be used to selectively control variations in the average polysilicon perimeter density of different regions of a chip and, thereby to selectively control certain performance parameter variations between functional devices located in those different regions.

    摘要翻译： 公开了至少部分地基于这些单元的已知多晶硅周边密度来布置集成电路设计的单个单元的方法。 也就是说，方法实施例使用已知单元的多晶硅周密度的知识来驱动这些单元在芯片上的放置（即，驱动楼层规划）。 方法实施例可以用于实现大致均匀的跨芯片多晶硅周边密度，并且由此限制可归因于多晶硅周边密度变化的功能器件之间的性能参数变化。 或者，方法实施例可以用于选择性地控制芯片的不同区域的平均多晶硅周长密度的变化，从而选择性地控制位于那些不同区域中的功能设备之间的某些性能参数变化。

    INTEGRATED CIRCUIT WITH UNIFORM POLYSILICON PERIMETER DENSITY, METHOD AND DESIGN STRUCTURE
    22.
    发明申请
    INTEGRATED CIRCUIT WITH UNIFORM POLYSILICON PERIMETER DENSITY, METHOD AND DESIGN STRUCTURE 有权
    具有均匀多晶硅密度的集成电路，方法和设计结构

    公开(公告)号：US20090278222A1

    公开(公告)日：2009-11-12

    申请号：US12117771

    申请日：2008-05-09

    申请人： Laura S. Chadwick ,  James A. Culp ,  David J. Hathaway ,  Anthony D. Polson

    发明人： Laura S. Chadwick ,  James A. Culp ,  David J. Hathaway ,  Anthony D. Polson

    IPC分类号： H01L27/00 ,  G06F17/50

    CPC分类号： H01L27/0207 ,  G06F17/5072

    摘要： Disclosed are embodiments of forming an integrated circuit with a desired decoupling capacitance and with the uniform and targeted across-chip polysilicon perimeter density. The method includes laying out functional blocks to form the circuit according to the design and also laying out one or more decoupling capacitor blocks to achieve the desired decoupling capacitance. Then, local polysilicon perimeter densities of the blocks are determined and, as necessary, the decoupling capacitor blocks are reconfigured in order to adjust for differences in the local polysilicon perimeter densities. This reconfiguring is performed in a manner that essentially maintains the desired decoupling capacitance. Due to the across-chip polysilicon perimeter density uniformity, functional devices in different regions of the chip will exhibit limited performance parameter variations (e.g., limited threshold voltage variations). Also disclosed herein are embodiments of an integrated circuit structure formed according to the method embodiments and a design structure for the integrated circuit.

    摘要翻译： 公开了形成具有期望的去耦电容并具有均匀和目标的跨芯片多晶硅周长密度的集成电路的实施例。 该方法包括根据设计布置功能块以形成电路，并且还布置一个或多个去耦电容器块以实现期望的去耦电容。 然后，确定块的局部多晶硅周边密度，并且根据需要重新配置去耦电容器块，以便调整局部多晶硅周边密度的差异。 这种重新配置以基本维持期望的去耦电容的方式执行。 由于跨芯片多晶硅周边密度均匀性，芯片的不同区域中的功能器件将表现出有限的性能参数变化（例如，限制阈值电压变化）。 本文还公开了根据方法实施例形成的集成电路结构和集成电路的设计结构的实施例。

    METHOD TO OPTIMIZE POWER BY TUNING THE SELECTIVE VOLTAGE BINNING CUT POINT
    24.
    发明申请
    METHOD TO OPTIMIZE POWER BY TUNING THE SELECTIVE VOLTAGE BINNING CUT POINT 失效
    通过调节选择性电压激活切割点来优化功率的方法

    公开(公告)号：US20090228843A1

    公开(公告)日：2009-09-10

    申请号：US12041729

    申请日：2008-03-04

    申请人： Theodoros E. Anemikos ,  Jeanne Bickford ,  Laura S. Chadwick ,  Susan K. Lichtensteiger ,  Anthony D. Polson

    发明人： Theodoros E. Anemikos ,  Jeanne Bickford ,  Laura S. Chadwick ,  Susan K. Lichtensteiger ,  Anthony D. Polson

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5045 ,  G06F2217/78

    摘要： A method of optimizing power usage in an integrated circuit design analyzes multiple operating speed cut points that are expected to be produced by the integrated circuit design. The operating speed cut points are used to divide identically designed integrated circuit devices after manufacture into relatively slow integrated circuits and relatively fast integrated circuit devices. The method selects an initial operating speed cut point to minimize a maximum power level of the relatively slow integrated circuits and relatively fast integrated circuit devices. The method then manufactures the integrated circuit devices using the integrated circuit design and tests the operating speeds and power consumption levels of the integrated circuit devices. Then, the method adjusts the initial cut point to a final cut point based on the testing, to minimize the maximum power level of the relatively slow integrated circuits and relatively fast integrated circuit devices.

    摘要翻译： 在集成电路设计中优化功率使用的方法分析了预期由集成电路设计产生的多个操作速度切割点。 操作速度切割点用于将制造后的相同设计的集成电路器件分成相对较慢的集成电路和相对较快的集成电路器件。 该方法选择初始操作速度切割点以使相对较慢的集成电路和相对快速的集成电路器件的最大功率电平最小化。 然后，该方法使用集成电路设计制造集成电路器件，并测试集成电路器件的工作速度和功耗水平。 然后，该方法基于测试将初始切割点调整到最终切割点，以使相对较慢的集成电路和相对较快的集成电路器件的最大功率电平最小化。

    High bandwidth low-latency semaphore mapped protocol (SMP) for multi-core systems on chips
    26.
    发明授权
    High bandwidth low-latency semaphore mapped protocol (SMP) for multi-core systems on chips 失效
    用于芯片上多核系统的高带宽低延迟信号量映射协议（SMP）

    公开(公告)号：US07765351B2

    公开(公告)日：2010-07-27

    申请号：US11684687

    申请日：2007-03-12

    申请人： Pascal A. Nsame ,  Anthony D. Polson ,  Nancy H. Pratt ,  Sebastian T. Ventrone

    发明人： Pascal A. Nsame ,  Anthony D. Polson ,  Nancy H. Pratt ,  Sebastian T. Ventrone

    IPC分类号： G06F12/00

    CPC分类号： G06F9/526 ,  G06F9/544 ,  G06F15/167

    摘要： A system and method for dynamically managing movement of semaphore data within the system. The system includes, but is no limited to, a plurality of functional units communicating over the network, a memory device communication with the plurality of functional units over the network, and at least one semaphore storage unit communicating with the plurality of functional unites and the memory device over the network. The plurality of functional units include a plurality of functional unit memory locations. The memory device includes a plurality of memory device memory locations. The at least one semaphore storage unit includes a plurality of semaphore storage unit memory locations. The at least one semaphore storage unit controls dynamic movement of the semaphore data among the plurality of functional unit memory locations, the plurality of memory device memory locations, the plurality of semaphore storage unit memory locations, and any combinations therof.

    摘要翻译： 用于动态管理系统内信号量数据移动的系统和方法。 该系统包括但不限于通过网络通信的多个功能单元，与网络上的多个功能单元的存储设备通信，以及与多个功能单元通信的至少一个信号量存储单元，以及 存储设备通过网络。 多个功能单元包括多个功能单元存储单元。 存储器件包括多个存储器件存储器位置。 所述至少一个信号量存储单元包括多个信号量存储单元存储单元。 所述至少一个信号量存储单元控制所述多个功能单元存储器位置，所述多个存储器设备存储器位置，所述多个信号量存储单元存储器位置中的所述信号量数据的动态移动以及所述多个功能单元存储单元的任何组合。

    SYSTEM AND METHOD TO OPTIMIZE SEMICONDUCTOR POWER BY INTEGRATION OF PHYSICAL DESIGN TIMING AND PRODUCT PERFORMANCE MEASUREMENTS
    28.
    发明申请
    SYSTEM AND METHOD TO OPTIMIZE SEMICONDUCTOR POWER BY INTEGRATION OF PHYSICAL DESIGN TIMING AND PRODUCT PERFORMANCE MEASUREMENTS 有权
    通过整合物理设计时序和产品性能测量来优化半导体功率的系统和方法

    公开(公告)号：US20090217221A1

    公开(公告)日：2009-08-27

    申请号：US12038320

    申请日：2008-02-27

    申请人： Theodoros E. ANEMIKOS ,  Jeanne P. Spence Bickford ,  Laura S. Chadwick ,  Susan K. Lichtensteiger ,  Anthony D. Polson

    发明人： Theodoros E. ANEMIKOS ,  Jeanne P. Spence Bickford ,  Laura S. Chadwick ,  Susan K. Lichtensteiger ,  Anthony D. Polson

    IPC分类号： G06F17/50

    CPC分类号： G01R31/3008

    摘要： A system and method is provided for optimizing semiconductor power by integration of physical design timing and product performance measurements. The method includes: establishing a timing run and identifying a sigma code for the timing run; establishing ring oscillator bins and respective code; identifying a required timing run for a second level assembly to satisfy a selected voltage bin; timing a product using the required timing run; testing a ring oscillator of the product using the timing to obtain physical design identification; recording the physical design identification and the sigma code for the timing run; and using the recorded physical design identification and the sigma code to set a voltage for the product to optimize power.

    摘要翻译： 提供了通过整合物理设计时序和产品性能测量来优化半导体功率的系统和方法。 该方法包括：建立定时运行并识别用于定时运行的西格玛码; 建立环形振荡器箱和相应的代码; 识别用于第二级组件以满足所选择的电压仓的所需时间运行; 使用所需的时间运行定时产品; 使用定时测试产品的环形振荡器以获得物理设计识别; 记录物理设计识别和时间运行的西格玛码; 并使用记录的物理设计标识和西格玛码来为产品设置电压以优化功率。