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    INTEGRATED TEST WAVEFORM GENERATOR (TWG) AND CUSTOMER WAVEFORM GENERATOR (CWG), DESIGN STRUCTURE AND METHOD
    2.
    发明申请
    INTEGRATED TEST WAVEFORM GENERATOR (TWG) AND CUSTOMER WAVEFORM GENERATOR (CWG), DESIGN STRUCTURE AND METHOD 有权
    集成测试波形发生器（TWG）和客户波形发生器（CWG），设计结构和方法

    公开(公告)号：US20090265677A1

    公开(公告)日：2009-10-22

    申请号：US12104461

    申请日：2008-04-17

    申请人： Gary D. Grise ,  Vikram Iyengar ,  David E. Lackey ,  David W. Milton

    发明人： Gary D. Grise ,  Vikram Iyengar ,  David E. Lackey ,  David W. Milton

    IPC分类号： H03K5/156 ,  G06F1/10 ,  G06F17/50

    CPC分类号： G06F17/505 ,  G06F1/10 ,  G06F2217/62 ,  H03K5/156

    摘要： Disclosed are embodiments of a clock generation circuit, a design structure for the circuit and an associated method that provide deskewing functions and that further provide precise timing for both testing and functional operations. Specifically, the embodiments incorporate a deskewer circuit that is capable of receiving waveform signals from both an external waveform generator and an internal waveform generator. The external waveform generator can generate and supply to the deskewer circuit a pair of waveform signals for functional operations. The internal waveform generator can be uniquely configured with control logic and counter logic for generating and supplying a pair of waveform signals to the deskewer circuit for any one of built-in self-test (BIST) operations, macro-test operations, other test operations or functional operations. The deskewer circuit can selectively gate an input clock signal with the waveform signals from either the external or internal waveform generator in order to generate the required output clock signal.

    摘要翻译： 公开了时钟发生电路的实施例，用于电路的设计结构和相关联的方法，其提供了偏移功能，并进一步为测试和功能操作提供精确的定时。 具体地说，这些实施例结合了能够从外部波形发生器和内部波形发生器接收波形信号的偏移电路。 外部波形发生器可以生成和提供一个用于功能操作的波形信号。 内部波形发生器可以独特地配置控制逻辑和计数器逻辑，用于为内置自检（BIST）操作，宏测试操作，其他测试操作中的任何一个生成和提供一对波形信号到电路板电路 或功能操作。 该偏移电路可以使用来自外部或内部波形发生器的波形信号选择性地输入输入时钟信号，以便产生所需的输出时钟信号。

    SCAN CHAIN CIRCUITRY THAT ENABLES SCAN TESTING AT FUNCTIONAL CLOCK SPEED
    3.
    发明申请
    SCAN CHAIN CIRCUITRY THAT ENABLES SCAN TESTING AT FUNCTIONAL CLOCK SPEED 审中-公开
    扫描链路电路以功能时钟速度扫描测试

    公开(公告)号：US20080005634A1

    公开(公告)日：2008-01-03

    申请号：US11427659

    申请日：2006-06-29

    申请人： Gary D. Grise ,  Steven F. Oakland ,  Mark R. Taylor

    发明人： Gary D. Grise ,  Steven F. Oakland ,  Mark R. Taylor

    IPC分类号： G01R31/28

    CPC分类号： G01R31/318552 ,  G01R31/318536

    摘要： Boundary scan circuitry that includes a plurality of scan cells that each contain two scan registers each for storing a respective test value. During on-chip or inter-chip testing, one of the scan registers is responsive to a functional clock signal so that the test cell generates transition delay test data having at least one state transition made at the speed of the functional clock signal. The transition delay test data allows the integrity of on-chip functional circuitry or the integrity of inter-chip circuitry to be verified at full functional speed.

    摘要翻译： 边界扫描电路包括多个扫描单元，每个扫描单元包含两个扫描寄存器，每个用于存储相应的测试值。 在片内或芯片间测试期间，其中一个扫描寄存器响应于功能时钟信号，使得测试单元产生具有以功能时钟信号速度进行的至少一个状态转换的转换延迟测试数据。 转换延迟测试数据允许在全功能速度下验证片上功能电路的完整性或芯片间电路的完整性。

    Clock edge grouping for at-speed test
    4.
    发明授权
    Clock edge grouping for at-speed test 失效
    用于速度测试的时钟分组

    公开(公告)号：US08538718B2

    公开(公告)日：2013-09-17

    申请号：US12967885

    申请日：2010-12-14

    申请人： Gary D. Grise ,  Vikram Iyengar ,  Douglas E. Sprague ,  Mark R. Taylor

    发明人： Gary D. Grise ,  Vikram Iyengar ,  Douglas E. Sprague ,  Mark R. Taylor

    IPC分类号： G06F19/00

    CPC分类号： G01R31/31726 ,  G01R31/31922

    摘要： A method of grouping clock domains includes: separating a plurality of test clocks into a plurality of domain groups by adding to each respective one of the plurality of domain groups those test clocks that originate from a same clock source and have a unique clock divider ratio; sorting the domain groups in decreasing order of size; and creating a plurality of parts by adding the respective one of the plurality of domain groups to a first one of the plurality of parts in which already present test clocks have a different clock source, and creating a new part and adding the respective one of the plurality of domain groups to the new part when test clocks present in the respective one of the plurality of domain groups originate from a respective same clock source and have a different clock divider ratio as test clocks present in all previously-created parts.

    摘要翻译： 一种对时钟域进行分组的方法包括：通过向多个域组中的每个相应的一个组分配来自相同时钟源的那些测试时钟并具有唯一的时钟分频比，将多个测试时钟分离成多个域组; 按照大小顺序排列域组; 以及通过将多个域组中的相应一个组合添加到已经存在的测试时钟具有不同时钟源的多个部分中的第一部分来创建多个部分，并且创建新部分并将相应的一个 当存在于多个域组中的相应一个域组中的相应一个域组中的测试时钟源自相应的相同时钟源并且具有不同的时钟分频比作为存在于所有先前创建的部分中的测试时钟时，多个域组到新部分。

    Method of increasing path coverage in transition test generation
    5.
    发明授权
    Method of increasing path coverage in transition test generation 失效
    在过渡测试生成中增加路径覆盖的方法

    公开(公告)号：US07793176B2

    公开(公告)日：2010-09-07

    申请号：US11696981

    申请日：2007-04-05

    申请人： Gary D. Grise ,  David J. Hathaway ,  Vikram Iyengar

    发明人： Gary D. Grise ,  David J. Hathaway ,  Vikram Iyengar

    IPC分类号： G01R31/28

    CPC分类号： G01R31/31715 ,  G01R31/31707 ,  G01R31/318328

    摘要： A method for automatically generating test patterns for digital logic circuitry using an automatic test pattern generation tool. The method includes generating test patterns and applying faulty behavior to various paths within the digital logic circuitry. As each circuit path is tested, tested circuit nodes along the circuit path are marked as “exercised.” Subsequent test paths are assembled by avoiding marked circuit nodes. In this manner, coverage of paths tested may be increased and many circuit nodes can be tested efficiently.

    摘要翻译： 一种使用自动测试图案生成工具自动生成数字逻辑电路测试图案的方法。 该方法包括生成测试模式并将故障行为应用于数字逻辑电路内的各种路径。 随着每个电路路径的测试，沿着电路路径的测试电路节点被标记为“行使”。随后的测试路径通过避免标记的电路节点进行组装。 以这种方式，可以增加测试路径的覆盖范围，并且可以有效地测试许多电路节点。

    APPARATUS AND METHOD FOR SELECTIVELY IMPLEMENTING LAUNCH OFF SCAN CAPABILITY IN AT SPEED TESTING
    6.
    发明申请
    APPARATUS AND METHOD FOR SELECTIVELY IMPLEMENTING LAUNCH OFF SCAN CAPABILITY IN AT SPEED TESTING 失效
    在速度测试中选择实现启动扫描能力的装置和方法

    公开(公告)号：US20090106608A1

    公开(公告)日：2009-04-23

    申请号：US11874972

    申请日：2007-10-19

    申请人： Gary D. Grise ,  Vikram Iyengar ,  David E. Lackey ,  Mark R. Taylor

    发明人： Gary D. Grise ,  Vikram Iyengar ,  David E. Lackey ,  Mark R. Taylor

    IPC分类号： G01R31/28

    CPC分类号： G01R31/318594 ,  G01R31/318541

    摘要： An apparatus for selectively implementing launch-off-scan capability in at-speed testing of integrated circuit devices includes a control device configured to selectively disable a master clock signal of a latch structure under test such that a pulse sequence of a system clock signal results in a slave-master-slave clock pulse sequence in the latch structure under test; wherein the control device utilizes the system clock signal as an input thereto and operates in a self-resetting fashion that is timing independent with respect to a scan chain.

    摘要翻译： 一种用于在集成电路装置的高速测试中选择性地实施发射扫描能力的装置包括控制装置，其被配置为选择性地禁用被测闩锁结构的主时钟信号，使得系统时钟信号的脉冲序列导致 被锁存结构中的从主从主时钟脉冲序列; 其中所述控制装置利用所述系统时钟信号作为其输入，并以相对于扫描链定时无关的自复位方式操作。

    METHOD FOR AUTOMATIC TEST PATTERN GENERATION FOR ONE TEST CONSTRAINT AT A TIME
    8.
    发明申请
    METHOD FOR AUTOMATIC TEST PATTERN GENERATION FOR ONE TEST CONSTRAINT AT A TIME 审中-公开
    一种用于一次测试约束的自动测试图形生成方法

    公开(公告)号：US20080222472A1

    公开(公告)日：2008-09-11

    申请号：US11684242

    申请日：2007-03-09

    申请人： Gary D. Grise ,  Vikram Iyengar ,  Mark R. Taylor

    发明人： Gary D. Grise ,  Vikram Iyengar ,  Mark R. Taylor

    IPC分类号： G01R31/28

    CPC分类号： G01R31/318307

    摘要： A method for automatically generating test patterns for an IC device includes initially generating a subset of available test patterns according to each of a plurality of test constraints for the IC device, determining an incremental amount of total test coverage of the IC device attributable to each of the test constraints as a result of the initially generated subset of test patterns therefor; determining the test constraint initially providing the largest amount of incremental test coverage, and thereafter generating another subset of test patterns therefor; and iteratively determining the current test constraint providing the largest amount of incremental test coverage, and continuing to generate additional test patterns therefor until one or more test exit criteria is reached.

    摘要翻译： 一种用于自动生成用于IC器件的测试图案的方法包括：根据IC器件的多个测试约束中的每一个，初始地生成可用测试图案的子集，确定归属于每个IC器件的IC器件的总测试覆盖的增量 作为最初生成的测试模式子集的结果的测试约束; 确定最初提供最大量的增量测试覆盖的测试约束，然后生成另一个测试模式子集; 并迭代地确定提供最大量的增量测试覆盖的当前测试约束，并且继续生成附加的测试模式，直到达到一个或多个测试退出标准。

    Integrated heat exchanger for memory module
    9.
    发明授权
    Integrated heat exchanger for memory module 有权
    内存模块集成热交换器

    公开(公告)号：US6025992A

    公开(公告)日：2000-02-15

    申请号：US249237

    申请日：1999-02-11

    申请人： Richard Charles Dodge ,  Kenneth Haskell Earl ,  Gary D. Grise ,  Douglas R. Guild ,  Karl D. Loughner ,  Jerzy Maria Zalesinski

    发明人： Richard Charles Dodge ,  Kenneth Haskell Earl ,  Gary D. Grise ,  Douglas R. Guild ,  Karl D. Loughner ,  Jerzy Maria Zalesinski

    IPC分类号： H01L23/373 ,  H05K7/20

    CPC分类号： H01L23/3733 ,  H01L2924/0002

    摘要： A circuit card unit comprising a memory card and attached heat exchanger comprising a thin, flexible, laminated strip of foil clad plastic, or wire mesh, affixed in thermally conductive contact to each card module and extended therefrom to facilitate removal of heat from the modules. In some embodiments, the exchanger strip extends from the modules on one side of the card to those of the other side in a self supporting, heat exchanger loop spaced over the memory card. In a somewhat more compact embodiment, the strip extends from modules on one card face, along the card itself, to the modules of the other card face. In a still further embodiment, the heat exchanger strip extends from the modules of the card to a heat sink such as the housing of the computer. Additionally, the heat exchanger strips may also function as a carrier for an identifying label printed on, or attached to, the planar surface of the strip.

    摘要翻译： 一种电路卡单元，包括存储卡和附接的热交换器，其包括薄的，柔性的箔包覆塑料或金属丝网层压带，其固定到每个卡模块的导热接触中并从其延伸，以便于从模块移除热量。 在一些实施例中，交换器条从卡的一侧上的模块延伸到在存储卡上间隔开的自支撑热交换器环中的另一侧的模块。 在一个更紧凑的实施例中，条带沿着卡本身从一个卡片面上的模块延伸到另一卡片面的模块。 在又一实施例中，热交换器条从卡的模块延伸到散热器，例如计算机的外壳。 此外，热交换器带还可以用作印刷在条带的平面上或附着于条的平面表面上的识别标签的载体。