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21.发明申请ROLLING TEXTURE CONTEXT DATA STRUCTURE FOR MAINTAINING TEXTURE DATA IN A MULTITHREADED IMAGE PROCESSING PIPELINE 失效在多路图像处理管道中维护纹理数据的滚动纹理语境数据结构公开(公告)号：US20110292063A1
公开(公告)日：2011-12-01
申请号：US12787110
申请日：2010-05-25
CPC分类号： G06T1/20
摘要： A multithreaded rendering software pipeline architecture utilizes a rolling texture context data structure to store multiple texture contexts that are associated with different textures that are being processed in the software pipeline. Each texture context stores state data for a particular texture, and facilitates the access to texture data by multiple, parallel stages in a software pipeline. In addition, texture contexts are capable of being “rolled”, or copied to enable different stages of a rendering pipeline that require different state data for a particular texture to separately access the texture data independently from one another, and without the necessity for stalling the pipeline to ensure synchronization of shared texture data among the stages of the pipeline.
摘要翻译： 多线程渲染软件流水线架构使用滚动纹理上下文数据结构来存储与在软件管线中处理的不同纹理相关联的多个纹理上下文。 每个纹理上下文存储特定纹理的状态数据，并且便于通过软件流水线中的多个并行级访问纹理数据。 此外，纹理上下文能够被“滚动”或被复制以实现需要用于特定纹理的不同状态数据的再现流水线的不同阶段以独立地彼此独立地访问纹理数据，并且不需要停止 管道，以确保管道的阶段之间共享纹理数据的同步。
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公开(公告)号：US07873701B2
公开(公告)日：2011-01-18
申请号：US12102038
申请日：2008-04-14
IPC分类号： G06F15/16
CPC分类号： G06F15/16
摘要： A design structure embodied in a machine readable medium is provided. Embodiments of the design structure include a network on chip (‘NOC’), the NOC comprising: integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controller, each IP block adapted to a router through a memory communications controller and a network interface controller, each memory communications controller controlling communication between an IP block and memory, and each network interface controller controlling inter-IP block communications through routers; the network organized into partitions, each partition including at least one IP block, each partition assigned exclusive access to a separate physical memory address space; and one or more applications executing on one or more of the partitions.
摘要翻译： 提供体现在机器可读介质中的设计结构。 该设计结构的实施例包括片上网络（NOC），NOC包括：集成处理器（“IP”）块，路由器，存储器通信控制器和网络接口控制器，每个IP块通过存储器适配于路由器 通信控制器和网络接口控制器，每个存储器通信控制器控制IP块和存储器之间的通信，以及控制通过路由器进行IP间块通信的每个网络接口控制器; 网络组织成分区，每个分区包括至少一个IP块，每个分区分配独占访问单独的物理内存地址空间; 以及在一个或多个分区上执行的一个或多个应用程序。
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公开(公告)号：US20100239186A1
公开(公告)日：2010-09-23
申请号：US12407340
申请日：2009-03-19
CPC分类号： G06T17/005 , G06T15/06 , G06T15/40
摘要： A circuit arrangement, program product and circuit arrangement utilize the known view orientation for an image frame to be rendered to reposition an Accelerated Data Structure (ADS) used during rendering to optimize the generation and/or use of the ADS, e.g., by transforming a scene from which an image frame is rendered to orient the scene relative to the view orientation prior to generating the ADS. A scene may be transformed, for example, to orient the view orientation within a single octant of the scene, with additional processing resources assigned to that octant to ensure sufficient processing resources are devoted to processing the primitives within the view orientation.
摘要翻译： 电路布置，程序产品和电路布置利用已知的视图方向来渲染图像帧以重新定位在渲染期间使用的加速数据结构（ADS），以优化ADS的生成和/或使用，例如通过将 在生成ADS之前，渲染图像帧以使场景相对于视图方向定向的场景。 例如，可以将场景变换为将景物方向定向在场景的单个八分圆内，附加的处理资源被分配给该八分圆，以确保足够的处理资源用于在视图取向中处理图元。
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24.发明申请Ordered And Unordered Network-Addressed Message Control With Embedded DMA Commands For A Network On Chip 审中-公开有序和无序的网络寻址消息控制与嵌入式DMA命令为片上网络公开(公告)号：US20090282419A1
公开(公告)日：2009-11-12
申请号：US12118315
申请日：2008-05-09
IPC分类号： G06F9/54
CPC分类号： H04L47/10 , H04L47/34 , H04L49/10 , H04L49/109 , H04L49/90
摘要： Data processing on a network on chip (‘NOC’) that includes integrated processor (‘IP’) blocks, routers, memory communications controllers, network interface controllers, and network-addressed message controllers, with each IP block adapted to a router through a memory communications controller, a network-addressed message controller, and a network interface controller, where each memory communications controller controlling communications between an IP block and memory, each network interface controller controlling inter-IP block communications through routers, with each IP block also adapted to the network by a low latency, high bandwidth application messaging interconnect comprising an inbox and an outbox.
摘要翻译： 包括集成处理器（“IP”）块，路由器，存储器通信控制器，网络接口控制器和网络寻址消息控制器的片上网络（“NOC”）上的数据处理，其中每个IP块通过 存储器通信控制器，网络寻址消息控制器和网络接口控制器，其中每个存储器通信控制器控制IP块和存储器之间的通信，每个网络接口控制器控制通过路由器的IP间块通信，每个IP块也被适配 通过包含收件箱和发件箱的低延迟，高带宽应用消息互连来连接到网络。
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公开(公告)号：US20090282226A1
公开(公告)日：2009-11-12
申请号：US12118039
申请日：2008-05-09
IPC分类号： G06F9/30
CPC分类号： G06F15/7825 , H04L49/109
摘要： A network on chip (‘NOC’) that includes IP blocks, routers, memory communications controllers, and network interface controllers, each IP block adapted to the network by an application messaging interconnect including an inbox and an outbox, one or more of the IP blocks including computer processors supporting a plurality of threads, the NOC also including an inbox and outbox controller configured to set pointers to the inbox and outbox, respectively, that identify valid message data for a current thread; and software running in the current thread that, upon a context switch to a new thread, is configured to: save the pointer values for the current thread, and reset the pointer values to identify valid message data for the new thread, where the inbox and outbox controller are further configured to retain the valid message data for the current thread in the boxes until context switches again to the current thread.
摘要翻译： 包括IP块，路由器，存储器通信控制器和网络接口控制器的片上网络（“NOC”），每个IP块通过包括收件箱和发件箱的应用消息传送互连网络适配到网络，IP网络中的一个或多个 块，包括支持多个线程的计算机处理器，NOC还包括分别设置指向当前线程的有效消息数据的收件箱和发送箱的指针的收件箱和发件箱控制器; 以及在当前线程中运行的软件，在上下文切换到新线程时，配置为：保存当前线程的指针值，并重置指针值以识别新线程的有效消息数据，其中收件箱和 发送箱控制器被进一步配置为将当前线程的有效消息数据保留在框中，直到上下文再次切换到当前线程。
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公开(公告)号：US20090135739A1
公开(公告)日：2009-05-28
申请号：US11945396
申请日：2007-11-27
IPC分类号： H04L12/28
CPC分类号： G06F15/7825 , H04L49/109 , H04L49/15 , H04L49/1546 , H04L49/3036 , H04L49/45
摘要： A network on chip (‘NOC’) that includes integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controllers, with each IP block adapted to a router through a memory communications controller and a network interface controller, where each memory communications controller controlling communications between an IP block and memory, and each network interface controller controlling inter-IP block communications through routers, with the network organized into partitions, each partition including at least one IP block, each partition assigned exclusive access to a separate physical memory address space and one or more applications executing on one or more of the partitions.
摘要翻译： 包括集成处理器（“IP”）块，路由器，存储器通信控制器和网络接口控制器的片上网络（“NOC”），每个IP块通过存储器通信控制器和网络接口控制器适配于路由器， 其中每个存储器通信控制器控制IP块和存储器之间的通信，以及控制通过路由器的IP间块通信的每个网络接口控制器，其中网络被组织成分区，每个分区包括至少一个IP块，每个分区被分配独占访问 单独的物理内存地址空间和在一个或多个分区上执行的一个或多个应用程序。
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27.发明授权Vector register file caching of context data structure for maintaining state data in a multithreaded image processing pipeline 有权用于在多线程图像处理管道中维护状态数据的上下文数据结构的向量寄存器文件缓存公开(公告)号：US08836709B2
公开(公告)日：2014-09-16
申请号：US13212418
申请日：2011-08-18
摘要： Frequently accessed state data used in a multithreaded graphics processing architecture is cached within a vector register file of a processing unit to optimize accesses to the state data and minimize memory bus utilization associated therewith. A processing unit may include a fixed point execution unit as well as a vector floating point execution unit, and a vector register file utilized by the vector floating point execution unit may be used to cache state data used by the fixed point execution unit and transferred as needed into the general purpose registers accessible by the fixed point execution unit, thereby reducing the need to repeatedly retrieve and write back the state data from and to an L1 or lower level cache accessed by the fixed point execution unit.
摘要翻译： 在多线程图形处理架构中使用的经常访问的状态数据被缓存在处理单元的向量寄存器文件中，以优化对状态数据的访问并最小化与其相关联的存储器总线利用。 处理单元可以包括固定点执行单元以及向量浮点执行单元，并且向量浮点执行单元使用的向量寄存器文件可用于对由固定点执行单元使用的状态数据进行缓存并转移为 需要进入由固定点执行单元访问的通用寄存器，从而减少了从固定点执行单元访问的L1或更低级高速缓存重复检索和回写状态数据的需要。
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28.发明授权Multithreaded software rendering pipeline with dynamic performance-based reallocation of raster threads 失效多线程软件渲染管道与基于动态性能的光栅线程重新分配公开(公告)号：US08587596B2
公开(公告)日：2013-11-19
申请号：US12824727
申请日：2010-06-28
IPC分类号： G06F15/80
CPC分类号： G06T1/20
摘要： A multithreaded rendering software pipeline architecture dynamically reallocates regions of an image space to raster threads based upon performance data collected by the raster threads. The reallocation of the regions typically includes resizing the regions assigned to particular raster threads and/or reassigning regions to different raster threads to better balance the relative workloads of the raster threads.
摘要翻译： 多线程渲染软件流水线架构基于栅格线程收集的性能数据，将图像空间的区域动态重新分配给栅格线程。 区域的重新分配通常包括调整分配给特定光栅线程的区域和/或重新分配区域到不同的光栅线程，以更好地平衡光栅线程的相对工作负载。
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公开(公告)号：US08413166B2
公开(公告)日：2013-04-02
申请号：US13212403
申请日：2011-08-18
IPC分类号： G06F3/00
CPC分类号： G06T1/20 , A63F2300/203 , A63F2300/64 , G06F9/544
摘要： A circuit arrangement and method implement impulse propagation in a multithreaded physics engine by assigning ownership of objects in a scene to individual threads and propagating impulses between objects that are in contact with one another by passing inter-thread impulse messages between the threads that own the contacting objects, while locally propagating impulses through objects using the threads to which such objects are assigned.
摘要翻译： 电路布置和方法通过将场景中的对象的所有权分配给单独的线程并且在彼此接触的对象之间传播脉冲来实现多线程物理引擎中的脉冲传播，所述对象通过在拥有所述接触的线程之间传递线间脉冲消息 对象，同时通过使用分配了这些对象的线程的对象来本地传播脉冲。
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公开(公告)号：US08248412B2
公开(公告)日：2012-08-21
申请号：US12407398
申请日：2009-03-19
IPC分类号： G06T15/40 , G06T1/00 , G06T15/00 , G06T15/50 , G06T15/60 , G06T15/10 , G06T15/20 , G06T15/06
摘要： A circuit arrangement, program product and circuit arrangement utilize a textured bounding volume to reduce the overhead associated with generating and using an Accelerated Data Structure (ADS) in connection with physical rendering. In particular, a subset of the primitives in a scene may be mapped to surfaces of a bounding volume to generate textures on such surfaces that can be used during physical rendering. By doing so, the primitives that are mapped to the bounding volume surfaces may be omitted from the ADS to reduce the processing overhead associated with both generating the ADS and using the ADS during physical rendering, and furthermore, in many instances the size of the ADS may be reduced, thus reducing the memory footprint of the ADS, and often improving cache hit rates and reducing memory bandwidth.
摘要翻译： 电路布置，程序产品和电路布置利用纹理边界体积来减少与生成和使用结合物理渲染的加速数据结构（ADS）相关联的开销。 特别地，场景中的图元的子集可被映射到边界体积的表面，以在物理渲染期间使用的这些表面上生成纹理。 通过这样做，可以从ADS中省略映射到边界体积表面的原语，以减少在物理渲染期间生成ADS和使用ADS相关联的处理开销，此外，在许多情况下，ADS的大小 可以减少，从而减少ADS的内存占用，并且经常提高缓存命中率并减少内存带宽。
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