公开(公告)号：US07403620B2

公开(公告)日：2008-07-22

申请号：US10611254

申请日：2003-07-01

Applicant: Pierre-Yvan Liardet ,  Fabrice Romain ,  Yannick Teglia ,  Laurence Sirtori

Inventor： Pierre-Yvan Liardet ,  Fabrice Romain ,  Yannick Teglia ,  Laurence Sirtori

IPC: H04L9/00

CPC classification number: H04L9/0631 ,  H04L9/003 ,  H04L2209/046 ,  H04L2209/08

Abstract: A method of cyphering and/or decyphering, by an integrated circuit, of a digital input code by means of several keys, comprising: dividing the code into several data blocks of same dimensions; and applying to said blocks several turns of a cyphering or decyphering comprising submitting each block to at least one same non-linear transformation and of subsequently combining each block with a different key at each turn, the operands being masked, upon execution of the method, by at least one first random number having the size of the code and all the blocks of which have the same value by combining, by an XOR-type function, the input and output blocks of the non-linear transformation with said random number.

Abstract translation: 一种通过集成电路对几个键进行数字输入代码的连接和/或解粘的方法，包括：将代码划分成相同尺寸的多个数据块; 以及向所述块应用多个匝数或次衰减，包括将每个块提交至少一个相同的非线性变换，并且随后在每一匝上将每个块与不同的密钥组合，所述操作数被屏蔽，在执行该方法时， 通过由XOR类型函数组合具有所述随机数的非线性变换的输入和输出块的具有代码大小和其所有块具有相同值的至少一个第一随机数。

公开(公告)号：US20070206785A1

公开(公告)日：2007-09-06

申请号：US11713887

申请日：2007-03-05

Applicant: Fabrice Romain

Inventor： Fabrice Romain

IPC: H04L9/28

CPC classification number: H04L9/005 ,  G06F7/723 ,  G06F7/725 ,  G06F2207/7223 ,  H04L9/003 ,  H04L2209/046

Abstract: A method for masking a digital quantity used by a calculation executed by an electronic circuit and including several iterations, each including at least one operation which is a function of at least one value depending on the digital quantity, the method including at least one first step of displacement of at least one operand of the operation in a storage element selected independently from the value.

Abstract translation: 一种用于屏蔽由电子电路执行的计算所使用的数字量的方法，包括几次迭代，每个迭代包括至少一个与数字量有关的至少一个值的函数，该方法包括至少一个第一步骤 在与该值独立地选择的存储元件中的操作的至少一个操作数的位移。

公开(公告)号：US20070043993A1

公开(公告)日：2007-02-22

申请号：US11402650

申请日：2006-04-11

Applicant: Fabrice Romain ,  Alain Pomet

Inventor： Fabrice Romain ,  Alain Pomet

IPC: G06F11/00 ,  G01R31/28

CPC classification number: G07F7/1008 ,  G06F21/75 ,  G06F21/77 ,  G06F21/79 ,  G06K19/073 ,  G06Q20/341 ,  G07F7/082 ,  H04L9/004

Abstract: A method and a circuit for protecting an integrated circuit against an extraction of data read from at least one memory, comprising the steps of comparing each data word to be output from the integrated circuit with at least one value stored in this circuit, and generating an error signal in case of an identity between the value and the data waiting to be output.

Abstract translation: 一种用于保护集成电路以防止从至少一个存储器读取的数据的提取的方法和电路，包括以下步骤：将从集成电路输出的每个数据字与存储在该电路中的至少一个值进行比较， 在值和等待输出的数据之间存在身份的情况下的错误信号。

公开(公告)号：US06581084B1

公开(公告)日：2003-06-17

申请号：US09483343

申请日：2000-01-14

Applicant: Fabrice Romain ,  Guy Monier ,  Marie-Noëlle Lepareux

Inventor： Fabrice Romain ,  Guy Monier ,  Marie-Noëlle Lepareux

IPC: G06F772

CPC classification number: G06F7/5275 ,  G06F7/724

Abstract: A multiplication circuit with an accumulator is provided. The multiplication circuit includes first latch circuits, second latch circuits, and elementary adders that are cascade-coupled to one another in series through the first latch circuits. Each of the adders has its carry output coupled to one of its inputs through one of the second latch circuits. Additionally, cancellation circuitry cancels the contents of each of the second latch circuits at least during selected multiplication operations so as to carry out multiplication operations in a Galois field. In some preferred embodiments, the cancellation circuitry includes a logic gate that receives a selection signal indicating the mode of operation, and the logic gate sets and holds the second latch circuits at zero when the selection signal indicates that the multiplication operation is to be done in a Galois field. In other preferred embodiments, the cancellation circuitry includes logic gates that are each associated with a pair formed by one of the adders and the associated second latch circuit. Also provided is a method for performing a multiplication operation in a Galois field using a multiplication circuit with an accumulator.

Abstract translation: 提供了具有累加器的乘法电路。 乘法电路包括通过第一锁存电路串联耦合的第一锁存电路，第二锁存电路和基本加法器。 每个加法器通过其中一个第二锁存电路将其进位输出耦合到其输入之一。 另外，消除电路至少在选择的乘法运算期间取消每个第二锁存电路的内容，以便在伽罗瓦域中执行乘法运算。 在一些优选实施例中，消除电路包括接收指示操作模式的选择信号的逻辑门，并且当选择信号指示要进行乘法运算时，逻辑门将第二锁存电路设置并保持为零 伽罗瓦领域。 在其它优选实施例中，消除电路包括逻辑门，每个逻辑门与由加法器和相关联的第二锁存电路之一形成的对相关联。 还提供了一种使用具有累加器的乘法电路在伽罗瓦域中执行乘法运算的方法。

公开(公告)号：US06424987B1

公开(公告)日：2002-07-23

申请号：US09256334

申请日：1999-02-19

Applicant: Fabrice Romain

Inventor： Fabrice Romain

IPC: G06F700

CPC classification number: G06F7/5324 ,  G06F7/49931 ,  G06F7/722 ,  G06F7/727 ,  G06F7/728

Abstract: The operation Y0=(X*J0) mod 2Bt is implemented directly within a coprocessor to eliminate the need for, a register of Bt=m*k bits within the coprocessor. This eliminated register enables the storage of a data element during the computation of Y0. The operation S=A*B mod 2m*k is implemented with a circuit including at least three registers and a multiplication circuit. One of the registers simultaneously stores S and an intermediate result. To improve the method, a second multiplication circuit and registers of variable sizes are used.

Abstract translation: 操作Y0 =（X * J0）mod 2Bt直接在协处理器内实现，从而不需要协处理器内的Bt = m * k位的寄存器。 该消除的寄存器使得在计算Y0期间可以存储数据元素。 使用包括至少三个寄存器和乘法电路的电路来实现操作S = A * B mod 2m * k。 其中一个寄存器同时存储S和一个中间结果。 为了改进方法，使用第二乘法电路和可变大小的寄存器。

公开(公告)号：US06341299B1

公开(公告)日：2002-01-22

申请号：US09253681

申请日：1999-02-19

Applicant: Fabrice Romain

Inventor： Fabrice Romain

IPC: G06F748

CPC classification number: G06F7/5324 ,  G06F7/5443 ,  G06F7/728

Abstract: The computation time of modular operations on large-format data is improved by using a computation circuit integrated as a modular arithmetic coprocessor. The computation circuit carries out an S=A*B+C type operation, with S and C encoded on 2*Bt bits, and A and B encoded on Bt bits. To carry out this operation, a storage flip-flop circuit enables the storage of a possible overflow carry value at the end of an elementary computation, and reinserts this carry value during the following computation.

Abstract translation: 通过使用集成为模数算术协处理器的计算电路，提高了大格式数据模块化操作的计算时间。 计算电路执行S = A * B + C型操作，S和C编码在2 * Bt位上，A和B编码在Bt位上。 为了执行该操作，存储触发器电路能够在基本计算结束时存储可能的溢出进位值，并且在随后的计算期间重新插入该进位值。