公开(公告)号：US09030791B2

公开(公告)日：2015-05-12

申请号：US13910386

申请日：2013-06-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Manjunatha Govinda Prabhu ,  Mahadeva Iyer Natarajan

IPC: H02H9/00 ,  H02H9/04 ,  H02H1/04 ,  H02H3/22 ,  H02H9/06

CPC classification number: H02H9/046

Abstract: A circuit for electrostatic discharge (ESD) protection is disclosed. The circuit includes multiple transistors that are selectively turned on during an ESD event. An ESD sense circuit detects an ESD event and asserts signals to activate an ESD protection circuit which closes multiple protection transistors to dissipate current during the ESD event. During normal operation of the circuit, the signals are de-asserted, disabling the ESD protection circuit.

Abstract translation: 公开了一种用于静电放电（ESD）保护的电路。 电路包括在ESD事件期间选择性地导通的多个晶体管。 ESD感测电路检测ESD事件并断言信号以激活ESD保护电路，其关闭多个保护晶体管以在ESD事件期间耗散电流。 在电路正常工作期间，信号被取消置位，禁止ESD保护电路。

公开(公告)号：US20140362481A1

公开(公告)日：2014-12-11

申请号：US13910386

申请日：2013-06-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Manjunatha Govinda Prabhu ,  Mahadeva Iyer Natarajan

IPC: H02H9/04

CPC classification number: H02H9/046

Abstract: A circuit for electrostatic discharge (ESD) protection is disclosed. The circuit includes multiple transistors that are selectively turned on during an ESD event. An ESD sense circuit detects an ESD event and asserts signals to activate an ESD protection circuit which closes multiple protection transistors to dissipate current during the ESD event. During normal operation of the circuit, the signals are de-asserted, disabling the ESD protection circuit.

Abstract translation: 公开了一种用于静电放电（ESD）保护的电路。 电路包括在ESD事件期间选择性地导通的多个晶体管。 ESD感测电路检测ESD事件并断言信号以激活ESD保护电路，其关闭多个保护晶体管以在ESD事件期间耗散电流。 在电路正常工作期间，信号被取消置位，禁止ESD保护电路。

公开(公告)号：US10510663B2

公开(公告)日：2019-12-17

申请号：US15474354

申请日：2017-03-30

Applicant: GLOBALFOUNDRIES INC.

Inventor： Chien-Hsin Lee ,  Haojun Zhang ,  Mahadeva Iyer Natarajan

IPC: H01L23/528 ,  H01L23/522 ,  H01L23/60 ,  H01P1/18

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to transistor structures and methods of manufacture. The structure includes active metal lines separated by electrically floating metal layers which have a width less than a width of the active metal lines.

公开(公告)号：US10147715B2

公开(公告)日：2018-12-04

申请号：US15481202

申请日：2017-04-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chien-hsin Lee ,  Mahadeva Iyer Natarajan ,  Manjunatha Prabhu

IPC: H01L21/8234 ,  H01L27/02 ,  H01L29/74 ,  H01L29/66 ,  H01L29/78

Abstract: Methods to forming trigger-voltage tunable cascode transistors for an ESD protection circuit in FinFET IC devices and resulting devices. Embodiments include providing a substrate including adjacent first-type well areas, over the substrate, each pair of first-type well areas separated by a second-type well area; providing one or more junction areas in each first and second type well area, each junction area being a first type or a second type; forming fins, spaced from each other, perpendicular to and over the first and second type junction areas; and forming junction-type devices by forming electrical connections between the first and second type junction areas in the first-type well areas and the substrate, wherein a first-stage junction-type device in a first-type well area includes stacked first and second type junction areas, and wherein the first-stage junction-type device is adjacent a second-type well area including first and second type junction areas.

公开(公告)号：US10115718B2

公开(公告)日：2018-10-30

申请号：US15134942

申请日：2016-04-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Chien-Hsin Lee ,  Manjunatha Prabhu ,  Mahadeva Iyer Natarajan

IPC: H01L27/02 ,  H01L29/417 ,  H01L23/535 ,  H01L21/768 ,  G05B19/4097

Abstract: Methods, apparatus, and systems relating to a MOSFET with ESD resistance, specifically, to a semiconductor device comprising a field-effect transistor (FET) comprising a gate, a source, and a drain, all extending parallel to each other in a first direction; at least one source electrostatic discharge (ESD) protection circuit; a source terminal disposed above and in electrical contact with the at least one source ESD protection circuit, wherein the source terminal extends in the first direction; at least one drain ESD protection circuit; and a drain terminal disposed above and in electrical contact with the at least one drain ESD protection circuit, wherein the drain terminal extends in the first direction.

公开(公告)号：US10068895B2

公开(公告)日：2018-09-04

申请号：US14661202

申请日：2015-03-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chien-Hsin Lee ,  Xiangxiang Lu ,  Manjunatha Prabhu ,  Mahadeva Iyer Natarajan

IPC: H01L23/62 ,  H01L27/02 ,  H01L29/417

Abstract: High-voltage semiconductor devices with electrostatic discharge (ESD) protection and methods of fabrication are provided. The semiconductor devices include a plurality of transistors on a substrate patterned with one or more common gates extending across a portion of the substrate, and a plurality of first S/D contacts and a plurality of second S/D contacts associated with the common gate(s). The second S/D contacts are disposed over a plurality of carrier-doped regions within the substrate. One or more floating nodes are disposed above the substrate and, at least in part, between second S/D contacts to facilitate defining the plurality of carrier-doped regions within the substrate. For instance, the carrier-doped regions may be defined from a mask with a common carrier-region opening, with the floating node(s) intersecting the common carrier-region opening and facilitating defining, along with the common opening, the plurality of separate carrier-doped regions.

公开(公告)号：US20180226394A1

公开(公告)日：2018-08-09

申请号：US15427128

申请日：2017-02-08

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chien-Hsin Lee ,  Mahadeva Iyer Natarajan ,  Manjunatha Prahbu

IPC: H01L27/02 ,  H01L29/78 ,  H01L29/06 ,  H01L23/535

CPC classification number: H01L27/0262 ,  H01L23/535 ,  H01L29/0649 ,  H01L29/785 ,  H01L29/87

Abstract: A fin field effect transistor (FinFET) ESD device is disclosed. The device may include: a substrate; a silicon-controlled rectifier (SCR) over the substrate, the SCR including: a p-well region over the substrate; an n-well region laterally abutting the p-well region over the substrate; a first P+ doped region over the p-well region; a first N+ doped region over the p-well region; and a second N+ doped region over the p-well region; and a Schottky diode electrically coupled to the n-well region, wherein the Schottky diode spans the n-well region and the p-well region, and wherein the Schottky diode controls electrostatic discharge (ESD) between the second N+ doped region and the n-well region.

公开(公告)号：US20180219006A1

公开(公告)日：2018-08-02

申请号：US15423006

申请日：2017-02-02

Applicant: GLOBALFOUNDRIES INC.

Inventor： Chien-Hsin Lee ,  Mahadeva Iyer Natarajan ,  Manjunatha Prabhu

IPC: H01L27/02 ,  H01L29/78 ,  H01L29/74 ,  H01L29/87

CPC classification number: H01L27/0262 ,  H01L29/742 ,  H01L29/785 ,  H01L29/87

Abstract: Various embodiments include fin-type field effect transistor (FinFET) structures. In some cases, a FinFET structure includes: a substrate; a silicon-controlled rectifier (SCR) over the substrate, the SCR including: a p-well region and an adjacent n-well region over the substrate; and a negatively charged fin over the p-well region; and a Schottky diode electrically coupled with the SCR, the Schottky diode spanning between the p-well region and the n-well region, the Schottky diode for controlling electrostatic discharge (ESD) across the negatively charged fin and the n-well region.

公开(公告)号：US20180083441A1

公开(公告)日：2018-03-22

申请号：US15271058

申请日：2016-09-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Mahadeva Iyer Natarajan ,  Chien-Hsin Lee ,  Manjunatha Prabhu

IPC: H02H9/04 ,  H02H1/00 ,  H01L27/02

CPC classification number: H02H9/046 ,  H01L27/0255 ,  H01L27/0262 ,  H01L27/0266 ,  H01L27/0288 ,  H01L27/0292 ,  H02H1/0061

Abstract: Methods, apparatus, and systems relating to a semiconductor device having an ESD function for providing a first ESD current flow in a first path and a second ESD current flow in a second path. The semiconductor device includes a pad for at least one of receiving or transmitting an electrical signal; a victim circuit; an electrostatic discharge (ESD) protection device configured for receiving at least a portion of an ESD current resulting from an ESD event and for protecting the victim circuit from damage from the ESD current; an ESD current control module capable of receiving an ESD current resulting from the ESD event from the pad, wherein the ESD current control module is capable of directing a first ESD current portion through the ESD protection device and a second ESD current portion through the victim circuit. The semiconductor device also comprises a dissipation path for receiving the first and second ESD current portions and directing the first and second ESD current portions through the dissipation path to a ground node.

公开(公告)号：US09831236B2

公开(公告)日：2017-11-28

申请号：US14699134

申请日：2015-04-29

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Chien-Hsin Lee ,  Xiangxiang Lu ,  Mahadeva Iyer Natarajan

IPC: H01L23/62 ,  H01L27/02 ,  H01L27/088 ,  H01L29/06

CPC classification number: H01L27/0266 ,  H01L27/0292 ,  H01L27/088 ,  H01L29/0619

Abstract: An electro-static discharge (ESD) protection transistor device includes a plurality of transistor gates that extend parallel to one another in a first direction and a plurality of source/drain diffusion areas that extend parallel to one another in a second direction perpendicular to the first direction. Each source/drain diffusion area comprises a plurality of source/drain areas disposed between respective ones of the plurality of transistor gates. The ESD protection transistor device further includes a source contact positioned over each source area of the plurality of source areas and a drain contact positioned over each drain area of the plurality of drain areas. With respect to each source/drain diffusion area of the plurality of source/drain diffusion areas, the source contacts are offset from the drain contacts with respect to the first direction.