公开(公告)号：US20210057558A1

公开(公告)日：2021-02-25

申请号：US16548518

申请日：2019-08-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： David Pritchard ,  Heng Yang ,  Hongru Ren ,  Neha Nayyar ,  Manjunatha Prabhu ,  Elizabeth Strehlow ,  Salvatore Cimino

IPC: H01L29/76 ,  H01L29/10 ,  H01L29/08

Abstract: A planar transistor device is disclosed including a gate structure positioned above a semiconductor substrate, the semiconductor substrate comprising a substantially planar upper surface, a channel region, a source region, a drain region, and at least one layer of a two-dimensional (2D) material that is positioned in at least one of the source region, the drain region or the channel region, wherein the layer of 2D material has a substantially planar upper surface, a substantially planar bottom surface and a substantially uniform vertical thickness across an entire length of the layer of 2D material in the gate length direction and across an entire width of the layer of 2D material in the gate width direction, wherein the substantially planar upper surface and the substantially planar bottom surface of the layer of 2D material are positioned approximately parallel to a substantially planar surface of the semiconductor substrate.

公开(公告)号：US20190035780A1

公开(公告)日：2019-01-31

申请号：US16147303

申请日：2018-09-28

Applicant: GLOBALFOUNDRIES INC.

Inventor： Chien-Hsin Lee ,  Manjunatha Prabhu ,  Mahadeva Iyer Natarajan

IPC: H01L27/02 ,  H01L23/535 ,  H01L21/768 ,  H01L29/417 ,  G05B19/4097

CPC classification number: H01L27/0288 ,  G05B19/4097 ,  G05B2219/45031 ,  H01L21/76895 ,  H01L23/535 ,  H01L29/4175

Abstract: Methods, apparatus, and systems relating to a MOSFET with ESD resistance, specifically, to a semiconductor device comprising a field-effect transistor (FET) comprising a gate, a source, and a drain, all extending parallel to each other in a first direction; at least one source electrostatic discharge (ESD) protection circuit; a source terminal disposed above and in electrical contact with the at least one source ESD protection circuit, wherein the source terminal extends in the first direction; at least one drain ESD protection circuit; and a drain terminal disposed above and in electrical contact with the at least one drain ESD protection circuit, wherein the drain terminal extends in the first direction.

公开(公告)号：US10790276B2

公开(公告)日：2020-09-29

申请号：US16147303

申请日：2018-09-28

Applicant: GLOBALFOUNDRIES INC.

Inventor： Chien-Hsin Lee ,  Manjunatha Prabhu ,  Mahadeva Iyer Natarajan

IPC: H01L27/02 ,  H01L29/417 ,  H01L23/535 ,  H01L21/768 ,  G05B19/4097

Abstract: Methods, apparatus, and systems relating to a MOSFET with ESD resistance, specifically, to a semiconductor device comprising a field-effect transistor (FET) comprising a gate, a source, and a drain, all extending parallel to each other in a first direction; at least one source electrostatic discharge (ESD) protection circuit; a source terminal disposed above and in electrical contact with the at least one source ESD protection circuit, wherein the source terminal extends in the first direction; at least one drain ESD protection circuit; and a drain terminal disposed above and in electrical contact with the at least one drain ESD protection circuit, wherein the drain terminal extends in the first direction.

公开(公告)号：US10373946B2

公开(公告)日：2019-08-06

申请号：US16038532

申请日：2018-07-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Chien-Hsin Lee ,  Mahadeva Iyer Natarajan ,  Manjunatha Prabhu

IPC: H01L27/02 ,  H01L29/78 ,  H01L29/74 ,  H01L29/861 ,  H01L29/06

Abstract: Various embodiments include fin-type field effect transistor (FinFET) structures. In some cases, a FinFET structure includes: a p-type substrate; a silicon-controlled rectifier (SCR) over the p-type substrate, the SCR including: a p-well region and an adjacent n-well region over the substrate; and a negatively charged fin over the p-well region; and a Schottky diode electrically coupled with the SCR, the Schottky diode including a gate in the n-well region, the Schottky diode positioned to mitigate electrostatic discharge (ESD) across the negatively charged fin and the n-well region in response to application of a forward voltage across the gate.

公开(公告)号：US10083952B2

公开(公告)日：2018-09-25

申请号：US15423006

申请日：2017-02-02

Applicant: GLOBALFOUNDRIES INC.

Inventor： Chien-Hsin Lee ,  Mahadeva Iyer Natarajan ,  Manjunatha Prabhu

IPC: H01L29/66 ,  H01L27/02 ,  H01L29/78 ,  H01L29/74 ,  H01L29/87

CPC classification number: H01L27/0262 ,  H01L29/0649 ,  H01L29/742 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/861

Abstract: Various embodiments include fin-type field effect transistor (FinFET) structures. In some cases, a FinFET structure includes: a substrate; a silicon-controlled rectifier (SCR) over the substrate, the SCR including: a p-well region and an adjacent n-well region over the substrate; and a negatively charged fin over the p-well region; and a Schottky diode electrically coupled with the SCR, the Schottky diode spanning between the p-well region and the n-well region, the Schottky diode for controlling electrostatic discharge (ESD) across the negatively charged fin and the n-well region.

公开(公告)号：US20170309615A1

公开(公告)日：2017-10-26

申请号：US15134942

申请日：2016-04-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Chien-Hsin Lee ,  Manjunatha Prabhu ,  Mahadeva Iyer Natarajan

IPC: H01L27/02 ,  H01L23/535 ,  G05B19/4097 ,  H01L21/768 ,  H01L29/417

CPC classification number: H01L27/0288 ,  G05B19/4097 ,  G05B2219/45031 ,  H01L21/76895 ,  H01L23/535 ,  H01L29/4175

Abstract: Methods, apparatus, and systems relating to a MOSFET with ESD resistance, specifically, to a semiconductor device comprising a field-effect transistor (FET) comprising a gate, a source, and a drain, all extending parallel to each other in a first direction; at least one source electrostatic discharge (ESD) protection circuit; a source terminal disposed above and in electrical contact with the at least one source ESD protection circuit, wherein the source terminal extends in the first direction; at least one drain ESD protection circuit; and a drain terminal disposed above and in electrical contact with the at least one drain ESD protection circuit, wherein the drain terminal extends in the first direction.

公开(公告)号：US10741542B2

公开(公告)日：2020-08-11

申请号：US16055365

申请日：2018-08-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chien-Hsin Lee ,  Xiangxiang Lu ,  Manjunatha Prabhu ,  Mahadeva Iyer Natarajan

IPC: H01L27/02 ,  H01L29/417 ,  H01L29/06 ,  H01L29/08 ,  H01L29/78

Abstract: High-voltage semiconductor devices with electrostatic discharge (ESD) protection and methods of fabrication are provided. The semiconductor devices include a plurality of transistors on a substrate patterned with one or more common gates extending across a portion of the substrate, and a plurality of first S/D contacts and a plurality of second S/D contacts associated with the common gate(s). The second S/D contacts are disposed over a plurality of carrier-doped regions within the substrate. One or more floating nodes are disposed above the substrate and, at least in part, between second S/D contacts to facilitate defining the plurality of carrier-doped regions within the substrate. For instance, the carrier-doped regions may be defined from a mask with a common carrier-region opening, with the floating node(s) intersecting the common carrier-region opening and facilitating defining, along with the common opening, the plurality of separate carrier-doped regions.

公开(公告)号：US10579774B2

公开(公告)日：2020-03-03

申请号：US16008176

申请日：2018-06-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Heng Lan Lau ,  Manjunatha Prabhu ,  Vikrant Kumar Chauhan ,  Shawn Walsh

IPC: G06F17/50

Abstract: In the disclosed design systems and methods, a schematic diagram includes nets and, connected to at least some nets, single-pin first and second imaginary devices. On any given net, a first imaginary device is associated with a tracking group property of the net (where nets in the same tracking group are in-phase) and a second imaginary device is associated with a voltage property of the net. A design layout generated based on the schematic diagram includes: net shapes representing the nets and, on net shapes that represent nets connected to the imaginary devices, tracking group and voltage labels corresponding to the tracking group and voltage properties. Net shape placement within the design layout and design rule checking are performed according to design rules that dictate placing net shapes with the same tracking group label together and further dictate minimum allowable spacing requirements depending upon the tracking group and voltage labels.

公开(公告)号：US20180323185A1

公开(公告)日：2018-11-08

申请号：US16038532

申请日：2018-07-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Chien-Hsin Lee ,  Mahadeva Iyer Natarajan ,  Manjunatha Prabhu

IPC: H01L27/02 ,  H01L29/87 ,  H01L29/78 ,  H01L29/74

CPC classification number: H01L27/0262 ,  H01L29/0649 ,  H01L29/742 ,  H01L29/785 ,  H01L29/861

Abstract: Various embodiments include fin-type field effect transistor (FinFET) structures. In some cases, a FinFET structure includes: a p-type substrate; a silicon-controlled rectifier (SCR) over the p-type substrate, the SCR including: a p-well region and an adjacent n-well region over the substrate; and a negatively charged fin over the p-well region; and a Schottky diode electrically coupled with the SCR, the Schottky diode including a gate in the n-well region, the Schottky diode positioned to mitigate electrostatic discharge (ESD) across the negatively charged fin and the n-well region in response to application of a forward voltage across the gate.

公开(公告)号：US09679888B1

公开(公告)日：2017-06-13

申请号：US15251632

申请日：2016-08-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chien-Hsin Lee ,  Mahadeva Iyer Natarajan ,  Manjunatha Prabhu

IPC: H01L27/02 ,  H01L27/06 ,  H01L23/528

CPC classification number: H01L27/0266 ,  H01L23/5286 ,  H01L27/0262 ,  H01L27/0288 ,  H01L27/0292 ,  H01L27/0623

Abstract: An electrostatic discharge (ESD) device for an integrated circuit includes a substrate having a longitudinally extending fin dispose thereon. A first n-type FinFET (NFET) is disposed within the fin. The NFET includes an n-type source, an n-type drain and a p-well disposed within the substrate under the source and drain. A p-type FinFET (PFET) is disposed within the fin. The PFET includes a p-type source/drain region and an n-well disposed within the substrate under the source/drain region. The n-well and p-well are located proximate enough to each other to form an np junction therebetween. The p-type source/drain region of the PFET and the n-type drain of the NFET are electrically connected to a common input node.