公开(公告)号：US20180083441A1

公开(公告)日：2018-03-22

申请号：US15271058

申请日：2016-09-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Mahadeva Iyer Natarajan ,  Chien-Hsin Lee ,  Manjunatha Prabhu

IPC: H02H9/04 ,  H02H1/00 ,  H01L27/02

CPC classification number: H02H9/046 ,  H01L27/0255 ,  H01L27/0262 ,  H01L27/0266 ,  H01L27/0288 ,  H01L27/0292 ,  H02H1/0061

Abstract: Methods, apparatus, and systems relating to a semiconductor device having an ESD function for providing a first ESD current flow in a first path and a second ESD current flow in a second path. The semiconductor device includes a pad for at least one of receiving or transmitting an electrical signal; a victim circuit; an electrostatic discharge (ESD) protection device configured for receiving at least a portion of an ESD current resulting from an ESD event and for protecting the victim circuit from damage from the ESD current; an ESD current control module capable of receiving an ESD current resulting from the ESD event from the pad, wherein the ESD current control module is capable of directing a first ESD current portion through the ESD protection device and a second ESD current portion through the victim circuit. The semiconductor device also comprises a dissipation path for receiving the first and second ESD current portions and directing the first and second ESD current portions through the dissipation path to a ground node.

公开(公告)号：US09653454B1

公开(公告)日：2017-05-16

申请号：US15215043

申请日：2016-07-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chien-hsin Lee ,  Mahadeva Iyer Natarajan ,  Manjunatha Prabhu

IPC: H01L21/336 ,  H01L27/02 ,  H01L29/74 ,  H01L29/66

CPC classification number: H01L27/0255 ,  H01L21/823431 ,  H01L27/0259 ,  H01L27/0262 ,  H01L29/66371 ,  H01L29/7408 ,  H01L29/785

Abstract: Methods to forming trigger-voltage tunable cascode transistors for an ESD protection circuit in FinFET IC devices and resulting devices. Embodiments include providing a substrate including adjacent first-type well areas, over the substrate, each pair of first-type well areas separated by a second-type well area; providing one or more junction areas in each first and second type well area, each junction area being a first type or a second type; forming fins, spaced from each other, perpendicular to and over the first and second type junction areas; and forming junction-type devices by forming electrical connections between the first and second type junction areas in the first-type well areas and the substrate, wherein a first-stage junction-type device in a first-type well area includes stacked first and second type junction areas, and wherein the first-stage junction-type device is adjacent a second-type well area including first and second type junction areas.