公开(公告)号：US20210242335A1

公开(公告)日：2021-08-05

申请号：US16776930

申请日：2020-01-30

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Jagar Singh ,  Alexander L. Martin ,  Alexander M. Derrickson

IPC: H01L29/735 ,  H01L21/285 ,  H01L29/10 ,  H01L21/308 ,  H01L29/08 ,  H01L29/66 ,  H01L29/06 ,  H01L21/266 ,  H01L21/265 ,  H01L29/45 ,  H01L21/3065

Abstract: Embodiments of the disclosure provide an integrated circuit (IC) structure, including: a semiconductor base on a first portion of a raised region of an insulative layer; a first inner emitter/collector (E/C) material on a second portion of the raised region of the insulative layer, wherein the inner E/C material is directly horizontally between the semiconductor base and a sidewall of the raised region; and a first outer E/C material on a first non-raised region of the insulative layer, wherein an upper portion of the first outer E/C material is adjacent the first inner E/C material.

公开(公告)号：US12176426B2

公开(公告)日：2024-12-24

申请号：US17657154

申请日：2022-03-30

Applicant: GlobalFoundries U.S. Inc.

Inventor： Hong Yu ,  Alexander M. Derrickson ,  Judson R. Holt

IPC: H01L29/73 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66

Abstract: Embodiments of the disclosure provide a bipolar transistor structure including a semiconductor fin on a substrate. The semiconductor fin has a first doping type, a length in a first direction, and a width in a second direction perpendicular to the first direction. A first emitter/collector (E/C) material is adjacent a first sidewall of the semiconductor fin along the width of the semiconductor fin. The first E/C material has a second doping type opposite the first doping type. A second E/C material is adjacent a second sidewall of the semiconductor fin along the width of the semiconductor fin. The second E/C material has the second doping type. A width of the first E/C material is different from a width of the second E/C material.

公开(公告)号：US11888050B2

公开(公告)日：2024-01-30

申请号：US17457325

申请日：2021-12-02

Applicant: GlobalFoundries U.S. Inc.

Inventor： John L. Lemon ,  Alexander M. Derrickson ,  Haiting Wang ,  Judson R. Holt

IPC: H01L29/73 ,  H01L29/735 ,  H01L29/66 ,  H01L29/10

CPC classification number: H01L29/735 ,  H01L29/1008 ,  H01L29/6625

Abstract: Embodiments of the disclosure provide a lateral bipolar transistor structure with inner and outer spacers, and related methods. A lateral bipolar transistor structure may have an emitter/collector (E/C) layer over an insulator. The E/C layer has a first doping type. A first base layer is on the insulator and adjacent the E/C layer. The first base layer has a second doping type opposite the first doping type. A second base layer is on the first base layer and having the second doping type. A dopant concentration of the second base layer is greater than a dopant concentration of the first base layer. An inner spacer is on the E/C layer and adjacent the second base layer. An outer spacer is on the E/C layer and adjacent the inner spacer.

公开(公告)号：US11862717B2

公开(公告)日：2024-01-02

申请号：US17456395

申请日：2021-11-24

Applicant: GlobalFoundries U.S. Inc.

Inventor： Vibhor Jain ,  John J. Pekarik ,  Alvin J. Joseph ,  Alexander M. Derrickson ,  Judson R. Holt

IPC: H01L29/66 ,  H01L29/735 ,  H01L29/08 ,  H01L29/15 ,  H01L29/10

CPC classification number: H01L29/735 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/1008 ,  H01L29/158 ,  H01L29/6625

Abstract: Embodiments of the disclosure provide a lateral bipolar transistor structure with a superlattice layer and methods to form the same. The bipolar transistor structure may have a semiconductor layer of a first single crystal semiconductor material over an insulator layer. The semiconductor layer includes an intrinsic base region having a first doping type. An emitter/collector (E/C) region may be adjacent the intrinsic base region and may have a second doping type opposite the first doping type. A superlattice layer is on the E/C region of the semiconductor layer. A raised E/C terminal, including a single crystal semiconductor material, is on the superlattice layer. The superlattice layer separates the E/C region from the raised E/C terminal.

公开(公告)号：US20230063301A1

公开(公告)日：2023-03-02

申请号：US17557176

申请日：2021-12-21

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Alexander M. Derrickson ,  Arkadiusz Malinowski ,  Jagar Singh ,  Mankyu Yang ,  Judson R. Holt

IPC: H01L29/737 ,  H01L29/165 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to annular bipolar transistors and methods of manufacture. The structure includes: a substate material; a collector region parallel to and above the substrate material; an intrinsic base region surrounding the collector region; an emitter region above the intrinsic base region; and an extrinsic base region contacting the intrinsic base region

公开(公告)号：US20230062194A1

公开(公告)日：2023-03-02

申请号：US17533882

申请日：2021-11-23

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Judson R. Holt ,  Vibhor Jain ,  Alexander M. Derrickson

IPC: H01L29/739 ,  H01L29/06 ,  H01L29/66

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a lateral bipolar transistor and methods of manufacture. The structure includes: an extrinsic base region; an emitter region on a first side of the extrinsic base region; a collector region on a second side of the extrinsic base region; and a gate structure comprising a gate oxide and a gate control in a same channel region as the extrinsic base region.

公开(公告)号：US11575029B2

公开(公告)日：2023-02-07

申请号：US17324183

申请日：2021-05-19

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Alexander M. Derrickson ,  Richard F. Taylor, III ,  Mankyu Yang ,  Alexander L. Martin ,  Judson R. Holt ,  Jagar Singh

IPC: H01L27/082 ,  H01L27/12 ,  H01L29/78 ,  H01L21/84 ,  H01L21/8238 ,  H01L21/768 ,  H01L29/735 ,  H01L29/739 ,  H01L29/66 ,  H01L29/08 ,  H01L29/10

Abstract: Disclosed is a semiconductor structure including at least one bipolar junction transistor (BJT), which is uniquely configured so that fabrication of the BJT can be readily integrated with fabrication of complementary metal oxide semiconductor (CMOS) devices on an advanced silicon-on-insulator (SOI) wafer. The BJT has an emitter, a base, and a collector laid out horizontally across an insulator layer and physically separated. Extension regions extend laterally between the emitter and the base and between the base and the collector and are doped to provide junctions between the emitter and the base and between the base and the collector. Gate structures are on the extension regions. The emitter, base, and collector are contacted. Optionally, the gate structures and a substrate below the insulator layer are contacted and can be biased to optimize BJT performance. Optionally, the structure further includes one or more CMOS devices. Also disclosed is a method of forming the structure.

公开(公告)号：US20220376093A1

公开(公告)日：2022-11-24

申请号：US17324183

申请日：2021-05-19

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Alexander M. Derrickson ,  Richard F. Taylor, III ,  Mankyu Yang ,  Alexander L. Martin ,  Judson R. Holt ,  Jagar Singh

IPC: H01L29/735 ,  H01L21/84 ,  H01L29/739 ,  H01L29/66 ,  H01L27/12 ,  H01L29/10 ,  H01L29/08

Abstract: Disclosed is a semiconductor structure including at least one bipolar junction transistor (BJT), which is uniquely configured so that fabrication of the BJT can be readily integrated with fabrication of complementary metal oxide semiconductor (CMOS) devices on an advanced silicon-on-insulator (SOI) wafer. The BJT has an emitter, a base, and a collector laid out horizontally across an insulator layer and physically separated. Extension regions extend laterally between the emitter and the base and between the base and the collector and are doped to provide junctions between the emitter and the base and between the base and the collector. Gate structures are on the extension regions. The emitter, base, and collector are contacted. Optionally, the gate structures and a substrate below the insulator layer are contacted and can be biased to optimize BJT performance. Optionally, the structure further includes one or more CMOS devices. Also disclosed is a method of forming the structure.

公开(公告)号：US11462632B2

公开(公告)日：2022-10-04

申请号：US17130121

申请日：2020-12-22

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Arkadiusz Malinowski ,  Alexander M. Derrickson ,  Ali Razavieh ,  Halting Wang

IPC: H01L29/735 ,  H01L29/08 ,  H01L29/66 ,  H01L29/10

Abstract: A non-uniform base width bipolar junction transistor (BJT) device includes: a semiconductor substrate, the semiconductor substrate having an upper surface; and a BJT device, the BJT device comprising a collector region, a base region, and an emitter region positioned in the semiconductor substrate, the base region being positioned between the collector region and the emitter region; the base region comprising a top surface and a bottom surface, wherein a first width of the top surface of the base region in a base width direction of the BJT device is greater than a second width of the bottom surface of the base region in the base width direction of the BJT device.

公开(公告)号：US11424349B1

公开(公告)日：2022-08-23

申请号：US17177490

申请日：2021-02-17

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Arkadiusz Malinowski ,  Alexander M. Derrickson ,  Judson R. Holt

IPC: H01L29/735 ,  H01L29/66 ,  H01L29/06

Abstract: A lateral bipolar junction transistor (BJT) device includes: an emitter region, a collector region, and a base region, the base region positioned between and laterally separating the emitter region and the collector region, the base region including an intrinsic base region; and a cavity formed in a semiconductor substrate and filled with an insulating material, the cavity physically separating a lower surface of the intrinsic base region from the semiconductor substrate.