公开(公告)号：US09619418B2

公开(公告)日：2017-04-11

申请号：US13399678

申请日：2012-02-17

Applicant: Gavin J. Stark

Inventor： Gavin J. Stark

IPC: G06F13/00 ,  G06F13/38

CPC classification number: G06F13/385

Abstract: An island-based network flow processor (IB-NFP) integrated circuit includes islands organized in rows. A configurable mesh event bus extends through the islands and is configured to form a local event ring. The configurable mesh event bus is configured with configuration information received via a configurable mesh control bus. The local event ring provides a communication path along which an event packet is communicated to each rectangular island along the local event ring. The local event ring involves event ring circuits and event ring segments. Upon each transition of a clock signal, an event packet moves through the ring from event ring segment to event ring segment. Event information and not packet data travels through the ring. The local event ring functions as a source-release ring in that only the event ring circuit that inserted the event packet onto the ring can delete the event packet from the ring.

公开(公告)号：US09237095B2

公开(公告)日：2016-01-12

申请号：US13399888

申请日：2012-02-17

Applicant: Gavin J. Stark ,  Steven W. Zagorianakos

Inventor： Gavin J. Stark ,  Steven W. Zagorianakos

IPC: G06F13/00 ,  H04L12/723 ,  G06F15/78

CPC classification number: H04L45/50 ,  G06F15/7867 ,  Y10T29/49124

Abstract: A reconfigurable, scalable and flexible island-based network flow processor integrated circuit architecture includes a plurality of rectangular islands of identical shape and size. The islands are disposed in rows, and a configurable mesh command/push/pull data bus extends through all the islands. The integrated circuit includes first SerDes I/O blocks, an ingress MAC island that converts incoming symbols into packets, an ingress NBI island that analyzes packets and generates ingress packet descriptors, a microengine (ME) island that receives ingress packet descriptors and headers from the ingress NBI and analyzes the headers, a memory unit (MU) island that receives payloads from the ingress NBI and performs lookup operations and stores payloads, an egress NBI island that receives the header portions and the payload portions and egress descriptors and performs egress scheduling, and an egress MAC island that outputs packets to second SerDes I/O blocks.

Abstract translation: 可重构，可扩展和灵活的基于岛的网络流处理器集成电路架构包括多个相同形状和大小的矩形岛。 岛排列成行，并且可配置的网格命令/推/拉数据总线延伸穿过所有岛。 该集成电路包括第一个SerDes I / O块，一个将输入符号转换成数据包的入口MAC岛，一个分析数据包并产生入口包描述符的入口NBI岛，一个微型引擎（ME）岛，接收入口数据包描述符和头 入口NBI并分析头部，存储单元（MU）岛，其从入口NBI接收有效载荷并执行查找操作并存储有效载荷;接收标题部分和有效载荷部分和出口描述符并执行出口调度的出口NBI岛， 以及向第二SerDes I / O块输出数据包的出口MAC岛。

公开(公告)号：US09098353B2

公开(公告)日：2015-08-04

申请号：US13675259

申请日：2012-11-13

Applicant: Gavin J. Stark

Inventor： Gavin J. Stark

IPC: G06F9/52 ,  G06F13/00 ,  G06F17/30 ,  G06F9/34 ,  G06F9/46

CPC classification number: G06F9/526 ,  G06F9/34 ,  G06F9/467 ,  G06F13/00 ,  G06F17/30

Abstract: A transactional memory (TM) receives a lookup command across a bus from a processor. The command includes a memory address, a starting bit position, and a mask size. In response to the command, the TM pulls an input value (IV). The memory address is used to read a word containing multiple result values (RVs) and multiple threshold values (TVs) from memory. A selecting circuit within the TM uses the starting bit position and mask size to select a portion of the IV. The portion of the IV is a lookup key value (LKV). The multiple TVs define multiple lookup key ranges. The TM determines which lookup key range includes the LKV. A RV is selected based upon the lookup key range determined to include the LKV. The lookup key range is determined by a lookup key range identifier circuit. The selected RV is selected by a result value selection circuit.

Abstract translation: 事务存储器（TM）从处理器接收总线上的查找命令。 该命令包括存储器地址，起始位位置和掩码大小。 响应该命令，TM拉动输入值（IV）。 存储器地址用于从存储器读取包含多个结果值（RV）和多个阈值（TV）的单词。 TM内的选择电路使用起始位位置和掩码大小来选择IV的一部分。 IV的部分是查询键值（LKV）。 多台电视定义了多个查找键范围。 TM确定哪个查找键范围包括LKV。 基于确定为包括LKV的查找关键字范围来选择RV。 查找键范围由查找键范围标识符电路确定。 所选择的RV由结果值选择电路选择。

公开(公告)号：US20150054547A1

公开(公告)日：2015-02-26

申请号：US13970599

申请日：2013-08-20

Applicant: Gavin J. Stark

Inventor： Gavin J. Stark

IPC: G06F7/00

CPC classification number: G06F9/467

Abstract: A hardware prefix reduction circuit includes a plurality of levels. Each level includes an input conductor, an output conductor, and a plurality of nodes. Each node includes a buffer and a storage device that stores a digital logic level. One node further includes an inverter. Another node further includes an AND gate with two non-inverting inputs. Another node further includes an AND gate with an inverting input and a non-inverting input. One bit of an input value, such as an internet protocol address, is communicated on the input conductor. The first level of the prefix reduction circuit includes two nodes and each subsequent level includes twice as many nodes as is included in the preceding level. A digital logic level is individually programmed into each storage device. The digital logic levels stored in the storage devices determines the prefix reduction algorithm implemented by the hardware prefix reduction circuit.

Abstract translation: 硬件前缀缩减电路包括多个电平。 每个级别包括输入导体，输出导体和多个节点。 每个节点包括存储数字逻辑电平的缓冲器和存储设备。 一个节点还包括一个逆变器。 另一节点还包括具有两个同相输入的“与”门。 另一个节点还包括具有反相输入和非反相输入的与门。 诸如互联网协议地址的输入值的一位在输入指示器上传送。 前缀缩减电路的第一级包括两个节点，并且每个后续级别包括在前一级中包括的两倍的节点。 数字逻辑电平被分别编程到每个存储设备中。 存储在存储装置中的数字逻辑电平确定由硬件前缀缩减电路实现的前缀缩减算法。

公开(公告)号：US20140025884A1

公开(公告)日：2014-01-23

申请号：US13552537

申请日：2012-07-18

Applicant: Gavin J. Stark ,  Benjamin J. Cahill

Inventor： Gavin J. Stark ,  Benjamin J. Cahill

IPC: G06F12/08

CPC classification number: G11C16/00 ,  G06F13/16 ,  G06F16/00 ,  G11C7/1006 ,  G11C7/1009 ,  G11C7/1039

Abstract: A transactional memory (TM) of an island-based network flow processor (IB-NFP) integrated circuit receives a Stats Add-and-Update (AU) command across a command mesh of a Command/Push/Pull (CPP) data bus from a processor. A memory unit of the TM stores a plurality of first values in a corresponding set of memory locations. A hardware engine of the TM receives the AU, performs a pull across other meshes of the CPP bus thereby obtaining a set of addresses, uses the pulled addresses to read the first values out of the memory unit, adds the same second value to each of the first values thereby generating a corresponding set of updated first values, and causes the set of updated first values to be written back into the plurality of memory locations. Even though multiple count values are updated, there is only one bus transaction value sent across the CPP bus command mesh.

Abstract translation: 基于岛屿的网络流处理器（IB-NFP）集成电路的事务存储器（TM）通过命令/推/拉（CPP）数据总线的命令网格接收统计添加和更新（AU）命令， 一个处理器 TM的存储单元将多个第一值存储在对应的一组存储器位置中。 TM的硬件引擎接收AU，执行CPP总线的其他网格的牵引，从而获得一组地址，使用拉动的地址将第一个值从存储器单元中读出，将相同的第二个值加到每个 所述第一值由此产生相应的一组更新的第一值，并且使得所述一组更新的第一值被写回到所述多个存储单元中。 即使更新了多个计数值，在CPP总线命令网格中只发送一个总线事务值。

公开(公告)号：US20140025858A1

公开(公告)日：2014-01-23

申请号：US13552555

申请日：2012-07-18

Applicant: Gavin J. Stark ,  Bruce Alexander Wilford

Inventor： Gavin J. Stark ,  Bruce Alexander Wilford

IPC: H03K17/00 ,  G06F13/40

CPC classification number: H03K17/00 ,  G06F9/467 ,  G06F13/40 ,  H04L45/745 ,  H04L45/748

Abstract: A hardware trie structure includes a tree of internal node circuits and leaf node circuits. Each internal node is configured by a corresponding multi-bit node control value (NCV). Each leaf node can output a corresponding result value (RV). An input value (IV) supplied onto input leads of the trie causes signals to propagate through the trie such that one of the leaf nodes outputs one of the RVs onto output leads of the trie. In a transactional memory, a memory stores a set of NCVs and RVs. In response to a lookup command, the NCVs and RVs are read out of memory and are used to configure the trie. The IV of the lookup is supplied to the input leads, and the trie looks up an RV. A non-final RV initiates another lookup in a recursive fashion, whereas a final RV is returned as the result of the lookup command.

Abstract translation: 硬件特里结构包括一棵内部节点电路和叶节点电路。 每个内部节点由相应的多位节点控制值（NCV）配置。 每个叶节点可以输出相应的结果值（RV）。 提供给特里的输入引线的输入值（IV）使得信号通过三通传播，使得一个叶节点将其中一个RV输出到该线索的输出引线。 在事务存储器中，存储器存储一组NCV和RV。 响应于查找命令，NCV和RV从存储器中读出并用于配置特里。 查询的IV被提供给输入引线，并且特技查找RV。 非最终RV以递归方式发起另一次查找，而作为查找命令的结果返回最终RV。

公开(公告)号：US20130219092A1

公开(公告)日：2013-08-22

申请号：US13399983

申请日：2012-02-17

Applicant: Gavin J. Stark ,  Jarod L. Oatley ,  Michael D. Secules ,  Ronald N. Fortino

Inventor： Gavin J. Stark ,  Jarod L. Oatley ,  Michael D. Secules ,  Ronald N. Fortino

IPC: G06F13/00

CPC classification number: G06F13/00 ,  G06F13/4022

Abstract: An island-based network flow processor (IB-NFP) integrated circuit includes islands organized in rows. A configurable mesh event bus extends through the islands and is configured to form one or more local event rings and a global event chain. The configurable mesh event bus is configured with configuration information received via a configurable mesh control bus. Each local event ring involves event ring circuits and event ring segments. In one example, an event packet being communicated along a local event ring reaches an event ring circuit. The event ring circuit examines the event packet and determines whether it meets a programmable criterion. If the event packet meets the criterion, then the event packet is inserted into the global event chain. The global event chain communicates the event packet to a global event manager that logs events and maintains statistics and other information.

Abstract translation: 基于岛屿的网络流处理器（IB-NFP）集成电路包括以行组织的岛屿。 可配置的mesh事件总线延伸穿过岛，并被配置为形成一个或多个本地事件环和全局事件链。 配置的mesh事件总线配置有通过可配置的网状控制总线接收的配置信息。 每个本地事件环包括事件环电路和事件环段。 在一个示例中，沿着本地事件环传送的事件分组到达事件环电路。 事件环电路检查事件数据包，并确定它是否符合可编程标准。 如果事件包满足标准，则将事件数据包插入到全局事件链中。 全局事件链将事件数据包传送给记录事件并维护统计信息和其他信息的全局事件管理器。

公开(公告)号：US20130219091A1

公开(公告)日：2013-08-22

申请号：US13399888

申请日：2012-02-17

Applicant: Gavin J. Stark ,  Steven W. Zagorianakos

Inventor： Gavin J. Stark ,  Steven W. Zagorianakos

IPC: G06F13/00 ,  H05K3/00

CPC classification number: H04L45/50 ,  G06F15/7867 ,  Y10T29/49124

Abstract: A reconfigurable, scalable and flexible island-based network flow processor integrated circuit architecture includes a plurality of rectangular islands of identical shape and size. The islands are disposed in rows, and a configurable mesh command/push/pull data bus extends through all the islands. The integrated circuit includes first SerDes I/O blocks, an ingress MAC island that converts incoming symbols into packets, an ingress NBI island that analyzes packets and generates ingress packet descriptors, a microengine (ME) island that receives ingress packet descriptors and headers from the ingress NBI and analyzes the headers, a memory unit (MU) island that receives payloads from the ingress NBI and performs lookup operations and stores payloads, an egress NBI island that receives the header portions and the payload portions and egress descriptors and performs egress scheduling, and an egress MAC island that outputs packets to second SerDes I/O blocks.

Abstract translation: 可重构，可扩展和灵活的基于岛的网络流处理器集成电路架构包括多个相同形状和大小的矩形岛。 岛排列成行，并且可配置的网格命令/推/拉数据总线延伸穿过所有岛。 该集成电路包括第一个SerDes I / O块，一个将输入符号转换成数据包的入口MAC岛，一个分析数据包并产生入口包描述符的入口NBI岛，一个微型引擎（ME）岛，接收入口数据包描述符和头 入口NBI并分析头部，存储单元（MU）岛，其从入口NBI接收有效载荷并执行查找操作并存储有效载荷;接收标题部分和有效载荷部分和出口描述符并执行出口调度的出口NBI岛， 以及向第二SerDes I / O块输出数据包的出口MAC岛。

公开(公告)号：US20130215899A1

公开(公告)日：2013-08-22

申请号：US13399846

申请日：2012-02-17

Applicant: Gavin J. Stark ,  Steven W. Zagorianakos ,  Ronald N. Fortino

Inventor： Gavin J. Stark ,  Steven W. Zagorianakos ,  Ronald N. Fortino

IPC: H04L12/56

CPC classification number: G06F13/4022 ,  G06F13/00 ,  H04L47/39 ,  H04L49/901

Abstract: An island-based integrated circuit includes a configurable mesh data bus. The data bus includes four meshes. Each mesh includes, for each island, a crossbar switch and radiating half links. The half links of adjacent islands align to form links between crossbar switches. A link is implemented as two distributed credit FIFOs. In one direction, a link portion involves a FIFO associated with an output port of a first island, a first chain of registers, and a second FIFO associated with an input port of a second island. When a transaction value passes through the FIFO and through the crossbar switch of the second island, an arbiter in the crossbar switch returns a taken signal. The taken signal passes back through a second chain of registers to a credit count circuit in the first island. The credit count circuit maintains a credit count value for the distributed credit FIFO.

Abstract translation: 基于岛的集成电路包括可配置的网状数据总线。 数据总线包括四个网格。 每个网格对于每个岛包括一个交叉开关和辐射半连接。 相邻岛屿的半连接对齐以形成交叉开关之间的连接。 链接被实现为两个分布式信用FIFO。 在一个方向上，链接部分涉及与第一岛的输出端口，第一寄存器链和与第二岛的输入端口相关联的第二FIFO相关联的FIFO。 当交易值通过FIFO并通过第二岛的交叉开关时，交叉开关中的仲裁器返回一个取得的信号。 所采集的信号通过第二个寄存器链回到第一个岛的信用计数电路。 信用计数电路维持分配信用FIFO的信用计数值。

公开(公告)号：US09612981B2

公开(公告)日：2017-04-04

申请号：US13399324

申请日：2012-02-17

Applicant: Gavin J. Stark

Inventor： Gavin J. Stark

IPC: G06F13/00 ,  G06F13/14

CPC classification number: G06F13/4068 ,  G06F13/14 ,  G06F13/36 ,  G06F13/4022 ,  G06F17/5068

Abstract: An island-based network flow processor (IB-NFP) integrated circuit includes rectangular islands disposed in rows. A configurable mesh data bus includes a command mesh, a pull-id mesh, and two data meshes. The configurable mesh data bus extends through all the islands. For each mesh, each island includes a centrally located crossbar switch and eight half links. Two half links extend to ports on the top edge of the island, a half link extends to a port on a right edge of the island, two half links extend to ports on the bottom edge of the island, and a half link extents to a port on the left edge of the island. Two additional links extend to functional circuitry of the island. The configurable mesh data bus is configurable to form a command/push/pull data bus over which multiple transactions can occur simultaneously on different parts of the integrated circuit.