公开(公告)号：US4445172A

公开(公告)日：1984-04-24

申请号：US221853

申请日：1980-12-31

申请人： Arthur Peters ,  Philip E. Stanley

发明人： Arthur Peters ,  Philip E. Stanley

IPC分类号： G06F12/08 ,  G06F13/00

CPC分类号： G06F12/0851

摘要： A cache memory including an even data store for storing data words associated with even address numbers and an odd data store for storing data words associated with odd address numbers, a local bus for transferring a low order data word and a high order data word simultaneously from the cache memory to a system element requesting the transfer of a pair of data words through the supplying of a single address number request, and a data steering multiplexer for supplying the data word associated with the memory request number, as outputted from either the odd or even cache data store to the low order data word transfer portion of the local bus and the other of the pair of data words outputted from the odd or even data store to the high order data word transfer portion of the local bus.

摘要翻译： 一种高速缓冲存储器，包括用于存储与偶数地址号码相关联的数据字的偶数数据存储器和用于存储与奇数地址号码相关联的数据字的奇数数据存储器，用于同时从低位数据字传输低位数据字的本地总线和高位数据字 高速缓冲存储器通过提供单个地址号码请求而请求传送一对数据字的系统元件，以及用于提供与存储器请求号相关联的数据字的数据导向复用器，从奇数或 甚至高速缓存数据存储到本地总线的低阶数据字传送部分，以及从奇数或偶数数据存储器输出到本地总线的高位数据字传送部分的一对数据字中的另一个。

公开(公告)号：US4414637A

公开(公告)日：1983-11-08

申请号：US224727

申请日：1981-01-13

申请人： Philip E. Stanley

发明人： Philip E. Stanley

IPC分类号： H03K5/06 ,  H03K5/04 ,  H03K5/159

CPC分类号： H03K5/06

摘要： A clock system for providing rectangular wave forms or wave trains, with each wave train having a selectable predetermined clock cycle period. A rectangular wave train is generated by a generator comprising a first delay line coupled to an inverter by using a multitapped second delay line to delay the rectangular wave train by selectable predetermined period. A control signal is formed which when fed into the generator produces a second rectangular wave train with a clock cycle period equal to the rectangular wave train clock cycle period plus the period of the second selected predetermined delay. By serially connecting a multitapped third delay line in series with the second delay line and by providing a first switch to select one of the outputs from said third delay line, the clock cycle period of the clock system may be adjusted. Use of a multitapped delay line for the first delay line and the addition of a second switch for selection among the various delayed signals of the first delay line, enable selective adjustment of clock pulse width.

摘要翻译： 一种用于提供矩形波形或波列的时钟系统，每个波段具有可选择的预定时钟周期周期。 由发生器产生矩形波列，该发生器包括通过使用多重第二延迟线连接到逆变器的第一延迟线，以通过可选择的预定周期延迟矩形波列。 形成控制信号，当馈送到发生器中时，产生具有等于矩形波列时钟周期周期的时钟周期周期加上第二选定预定延迟的周期的第二矩形波列。 通过串联连接与第二延迟线串联的多极化第三延迟线，并且通过提供第一开关来选择来自所述第三延迟线的输出之一，可以调整时钟系统的时钟周期周期。 对于第一延迟线使用多重延迟线和在第一延迟线的各种延迟信号之间添加用于选择的第二开关，使得能够选择性地调整时钟脉冲宽度。

公开(公告)号：US4348724A

公开(公告)日：1982-09-07

申请号：US140643

申请日：1980-04-15

申请人： David E. Cushing ,  Philip E. Stanley

发明人： David E. Cushing ,  Philip E. Stanley

IPC分类号： G06F9/28 ,  G06F9/22 ,  G06F9/26

CPC分类号： G06F9/265

摘要： A data processing system includes a first memory for storing microinstructions in a first plurality of storage locations and second memory for storing microinstructions in a second plurality of storage locations. A central processor executing a series of addressed microinstructions to control the functions performed by this system generates the address of the next microinstruction to be executed in series as well as a next address selection signal. Addressing circuitry concurrently applies the next address generated by the processor to address inputs of each of the first memory and the second memory. After a predetermined delay, either the first memory or the second memory is selected to output an address microinstruction responsive to the value of the next address selection signal.

摘要翻译： 数据处理系统包括用于存储第一多个存储位置中的微指令的第一存储器和用于在第二多个存储位置中存储微指令的第二存储器。 执行一系列寻址微指令以控制由该系统执行的功能的中央处理器产生要串行执行的下一个微指令的地址以及下一个地址选择信号。 寻址电路同时将由处理器产生的下一个地址应用于地址第一存储器和第二存储器中的每一个的输入。 在预定的延迟之后，选择第一存储器或第二存储器以响应于下一个地址选择信号的值来输出地址微指令。

公开(公告)号：US4099255A

公开(公告)日：1978-07-04

申请号：US749572

申请日：1976-12-10

申请人： Philip E. Stanley ,  William E. Woods

发明人： Philip E. Stanley ,  William E. Woods

IPC分类号： G06F9/48 ,  G06F1/04 ,  G06F11/00

CPC分类号： G06F9/4825

摘要： Interrupt service is enabled for either a real-time clock or watchdog timer time out condition. A mode register is provided to effectively enable or disable the interrupt apparatus and if enabled is coupled to enable a service register in response to repetitively occurring clock pulses. Each time the service register is enabled, a counter is changed in value until a predetermined value is indicated at which time interrupt service is enabled at an interrupt level specified by the operator. Further, facilities are provided for presetting the value of the counter in an expeditious manner.

摘要翻译： 中断服务启用了实时时钟或看门狗定时器超时条件。 提供模式寄存器以有效地启用或禁用中断装置，并且如果使能被耦合以使服务寄存器响应于重复出现的时钟脉冲。 每次服务寄存器被使能时，计数器的值被改变，直到指定了一个预定值，在该时间中断服务被允许在操作者指定的中断级别。 此外，还提供了一个快速预设柜台价值的设施。

公开(公告)号：US4020471A

公开(公告)日：1977-04-26

申请号：US591905

申请日：1975-06-30

申请人： William E. Woods ,  Philip E. Stanley

发明人： William E. Woods ,  Philip E. Stanley

IPC分类号： G06F13/26 ,  G06F9/18

CPC分类号： G06F13/26

摘要： In a data processing system, interrupt service is provided for any one of a plurality of interrupt sources which presents an interrupt signal which has a higher interrupt level than that of the currently active source. Interrupt flags are provided for each potential interrupt source, which flags are activated in response to the receipt of an interrupt signal from the interrupt source associated therewith. A scan for the highest interrupt level is made and interrupt service is provided for the interrupt source associated therewith.

摘要翻译： 在数据处理系统中，为多个中断源中的任何一个提供中断服务，该中断源提供具有比当前活动源更高的中断级别的中断信号。 为每个潜在的中断源提供中断标志，响应于从中断源接收到的中断信号，这些标志被激活。 对最高中断级进行扫描，并为与其相关联的中断源提供中断服务。

公开(公告)号：US3984820A

公开(公告)日：1976-10-05

申请号：US591966

申请日：1975-06-30

申请人： Philip E. Stanley ,  William E. Woods

发明人： Philip E. Stanley ,  William E. Woods

IPC分类号： G06F9/48 ,  G06F9/06

CPC分类号： G06F9/4831

摘要： A data processing system having a plurality of interrupt sources coupled to provide interrupt handling of a process currently executing at a specified interrupt level. A level change signal which may be generated by the process itself may change the specified level of such process to another level which may make such process less interruptable to other interrupt sources. The level change provided takes place without interrupting the execution of such process.

摘要翻译： 一种具有多个中断源的数据处理系统，其耦合以提供当前在指定中断级别执行的进程的中断处理。 可以由过程本身产生的电平变化信号可以将这种处理的指定级别改变到另一个级别，这可以使得这种处理对其他中断源的中断更少。 提供的级别更改在不中断执行此过程的情况下进行。