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公开(公告)号：US4467417A
公开(公告)日：1984-08-21
申请号：US302903
申请日：1981-09-16
CPC分类号： G06F9/30181 , G06F9/3016 , G06F9/325
摘要： A logic control system is disclosed for accommodating the flow of both procedural information and CPU (central processing unit) instructions from a central memory system to a CPU without compromising memory bandwidths or CPU execution speeds because of transfer delays or timing variances. Instruction modifications and plural task assignments are accommodated during instruction execution.
摘要翻译： 公开了一种逻辑控制系统，用于将过程信息和CPU（中央处理单元）指令的流程从中央存储器系统适应到CPU，而不会因为传输延迟或定时方差而危及存储器带宽或CPU执行速度。 在指令执行期间容纳指令修改和多任务分配。
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2.发明授权
公开(公告)号：US4349874A
公开(公告)日：1982-09-14
申请号：US140630
申请日：1980-04-15
CPC分类号： G06F12/0862 , G06F2212/6022
摘要： In a data processing system, a central processor unit requests procedural data words or non-procedural data words stored in the system memory. A control store device executes firmware instructions including a local bus field for controlling the transfer of the requested procedural data words and non-procedural data words to the central processor unit. The requested procedural data words and non-procedural data words are transferred to the central processing unit by an interfacing device including a data bus latch for receiving the procedural data words and non-procedural data words transferred from the memory, a prefetch buffer for storing up to four words, a first set of OR gate circuits for selectively transferring the procedural data words stored in the prefetch buffer to a procedural data multiplexer for assembling either a procedural data word or a procedure address, and a second set of OR gate circuits for selectively transferring either a procedural data word or non-procedural data word to the source bus or a procedural data address or non-procedural data address to the source bus for transfer to the central processor unit.
摘要翻译： 在数据处理系统中，中央处理器单元请求存储在系统存储器中的过程数据字或非程序数据字。 控制存储设备执行固件指令，其包括本地总线字段，用于控制所请求的过程数据字和非程序数据字向中央处理器单元的传送。 所请求的程序数据字和非程序数据字通过包括用于接收程序数据字的数据总线锁存器和从存储器传送的非程序数据字的接口装置传送到中央处理器，用于存储的预取缓冲器 四个字，第一组OR门电路，用于选择性地将存储在预取缓冲器中的程序数据字传送到程序数据多路复用器，用于组装程序数据字或程序地址，以及第二组OR门电路，用于选择性地 将程序数据字或非程序数据字传送到源总线或程序数据地址或非程序数据地址到源总线以传送到中央处理器单元。
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公开(公告)号：US4047247A
公开(公告)日：1977-09-06
申请号：US674517
申请日：1976-04-07
CPC分类号： G06F9/355
摘要： A final effective address of an operand is generated in a microprogrammed data processing system by use of a base address register which may include an unindexed address, an index register which may include an index address value, an instruction register which may include an instruction word, which instruction word provides control over the addressing of a control store dependent upon the state of a selected one of a plurality of test conditions. The addressed control store word provides signals for controlling the operation of the system, including the branching between such major operations as instruction fetching, addressing, reading, writing, and execution as well as branching between minor operations which are included in the major operations.
摘要翻译： 操作数的最终有效地址在微程序数据处理系统中通过使用可包括无索引地址的基址寄存器，可包括索引地址值的索引寄存器，可包括指令字的指令寄存器， 该指令字取决于多个测试条件中所选择的一个的状态来提供对控制存储器的寻址的控制。 寻址的控制存储字提供用于控制系统操作的信号，包括在诸如指令获取，寻址，读取，写入和执行之类的主要操作之间的分支以及在主要操作中包括的次要操作之间的分支。
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公开(公告)号：US4451883A
公开(公告)日：1984-05-29
申请号：US326260
申请日：1981-12-01
CPC分类号： G06F9/30032 , G06F9/30167
摘要： A data processing system includes a memory subsystem for storing operands and instructions and a central processing unit (CPU) for manipulating the operands by executing the instructions. The CPU includes a control store for generating signals for controlling the CPU operation. Shifters made up of multiplexers shift operands between an outer bus and a write bus in response to control store signals. The multiplexers shift the operands left or right 1, 2 or 4-bit positions including open shifts and circular shifts and also perform byte position shifting and twinning.
摘要翻译： 数据处理系统包括用于存储操作数和指令的存储器子系统和用于通过执行指令来操纵操作数的中央处理单元（CPU）。 CPU包括用于产生用于控制CPU操作的信号的控制存储器。 由复用器组成的移位器响应于控制存储信号在外部总线和写入总线之间移动操作数。 多路复用器将操作数向左或向右移位1,2或4位位置，包括开位移和循环移位，并且还执行字节位移和孪生。
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公开(公告)号：US4079451A
公开(公告)日：1978-03-14
申请号：US674698
申请日：1976-04-07
CPC分类号： G06F9/30018 , G06F12/04
摘要： A data processing system for providing word, byte or bit addressing. A word location in a memory device may be addressed based upon the contents of a base address register. Indirect addressing may be provided to another word location based upon a word index value in an index register. Effective byte or bit addressing of the addressed word is provided in response to byte and bit index values which are produced by means of the index register. An instruction word indicates the type of addressing and directs the use of different control words included in a control storage device in order to implement the desired operation.
摘要翻译： 一种用于提供字，字节或位寻址的数据处理系统。 可以基于基地址寄存器的内容来寻址存储器设备中的字位置。 可以基于索引寄存器中的单词索引值将间接寻址提供给另一单词位置。 响应于通过索引寄存器产生的字节和位索引值，提供寻址字的有效字节或位寻址。 指令字指示寻址的类型并指示使用包括在控制存储设备中的不同控制字，以便实现期望的操作。
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公开(公告)号：US4472773A
公开(公告)日：1984-09-18
申请号：US302897
申请日：1981-09-16
CPC分类号： G06F9/30
摘要： A decoding logic system in a logic control system of a data processing system is disclosed, wherein the data processing system is comprized of a main memory unit communicating with the logic control system by way of a common communication bus, and wherein the logic control system and a CPU (central processing unit) communicate by way of a local communication bus. In response to a CPU request, CPU instructions stored in the main memory unit are received by the logic decoding system, and presented to the CPU in such a manner as to accommodate both memory bit and CPU computed bit modifications to the instructions during instruction execution, while avoiding interruptions in CPU activity caused by information transfer delays internal to the logic decoding system. Instruction modification also may be effected by incrementing or decrementing the instructions under firmware control.
摘要翻译： 公开了一种数据处理系统的逻辑控制系统中的解码逻辑系统，其中数据处理系统由与公共通信总线与逻辑控制系统通信的主存储单元组成，其中逻辑控制系统和 CPU（中央处理单元）通过本地通信总线进行通信。 响应于CPU请求，存储在主存储器单元中的CPU指令由逻辑解码系统接收，并且以在指令执行期间容纳存储器位和CPU计算的位修改的方式呈现给CPU， 同时避免在逻辑解码系统内部的信息传输延迟引起的CPU活动中断。 也可以通过在固件控制下增加或减少指令来实现指令修改。
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7.发明授权Interrupt apparatus for enabling interrupt service in response to time out conditions 失效用于响应超时条件启用中断服务的中断装置
公开(公告)号：US4099255A
公开(公告)日：1978-07-04
申请号：US749572
申请日：1976-12-10
CPC分类号： G06F9/4825
摘要： Interrupt service is enabled for either a real-time clock or watchdog timer time out condition. A mode register is provided to effectively enable or disable the interrupt apparatus and if enabled is coupled to enable a service register in response to repetitively occurring clock pulses. Each time the service register is enabled, a counter is changed in value until a predetermined value is indicated at which time interrupt service is enabled at an interrupt level specified by the operator. Further, facilities are provided for presetting the value of the counter in an expeditious manner.
摘要翻译： 中断服务启用了实时时钟或看门狗定时器超时条件。 提供模式寄存器以有效地启用或禁用中断装置，并且如果使能被耦合以使服务寄存器响应于重复出现的时钟脉冲。 每次服务寄存器被使能时，计数器的值被改变，直到指定了一个预定值，在该时间中断服务被允许在操作者指定的中断级别。 此外，还提供了一个快速预设柜台价值的设施。
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公开(公告)号：US4020471A
公开(公告)日：1977-04-26
申请号：US591905
申请日：1975-06-30
CPC分类号： G06F13/26
摘要： In a data processing system, interrupt service is provided for any one of a plurality of interrupt sources which presents an interrupt signal which has a higher interrupt level than that of the currently active source. Interrupt flags are provided for each potential interrupt source, which flags are activated in response to the receipt of an interrupt signal from the interrupt source associated therewith. A scan for the highest interrupt level is made and interrupt service is provided for the interrupt source associated therewith.
摘要翻译： 在数据处理系统中，为多个中断源中的任何一个提供中断服务，该中断源提供具有比当前活动源更高的中断级别的中断信号。 为每个潜在的中断源提供中断标志，响应于从中断源接收到的中断信号，这些标志被激活。 对最高中断级进行扫描，并为与其相关联的中断源提供中断服务。
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9.发明授权Apparatus for changing the interrupt level of a process executing in a data processing system 失效用于改变在数据处理系统中执行的处理的中断级别的装置
公开(公告)号：US3984820A
公开(公告)日：1976-10-05
申请号：US591966
申请日：1975-06-30
CPC分类号： G06F9/4831
摘要： A data processing system having a plurality of interrupt sources coupled to provide interrupt handling of a process currently executing at a specified interrupt level. A level change signal which may be generated by the process itself may change the specified level of such process to another level which may make such process less interruptable to other interrupt sources. The level change provided takes place without interrupting the execution of such process.
摘要翻译： 一种具有多个中断源的数据处理系统，其耦合以提供当前在指定中断级别执行的进程的中断处理。 可以由过程本身产生的电平变化信号可以将这种处理的指定级别改变到另一个级别，这可以使得这种处理对其他中断源的中断更少。 提供的级别更改在不中断执行此过程的情况下进行。
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公开(公告)号：US4467416A
公开(公告)日：1984-08-21
申请号：US302898
申请日：1981-09-16
CPC分类号： G06F9/325 , G06F9/3016
摘要： A logic control system is disclosed for accommodating the flow of both procedural information and CPU (central processing unit) instructions from a central memory system to a CPU without compromising memory bandwidths or CPU execution speeds because of transfer delays or timing variances. Instruction modifications and plural task assignments are accommodated during instruction execution.
摘要翻译： 公开了一种逻辑控制系统，用于将过程信息和CPU（中央处理单元）指令的流程从中央存储器系统适应到CPU，而不会因为传输延迟或定时方差而危及存储器带宽或CPU执行速度。 在指令执行期间容纳指令修改和多任务分配。
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