-
公开(公告)号：US4467416A
公开(公告)日：1984-08-21
申请号：US302898
申请日：1981-09-16
CPC分类号： G06F9/325 , G06F9/3016
摘要： A logic control system is disclosed for accommodating the flow of both procedural information and CPU (central processing unit) instructions from a central memory system to a CPU without compromising memory bandwidths or CPU execution speeds because of transfer delays or timing variances. Instruction modifications and plural task assignments are accommodated during instruction execution.
摘要翻译： 公开了一种逻辑控制系统，用于将过程信息和CPU（中央处理单元）指令的流程从中央存储器系统适应到CPU，而不会因为传输延迟或定时方差而危及存储器带宽或CPU执行速度。 在指令执行期间容纳指令修改和多任务分配。
-
公开(公告)号：US4455606A
公开(公告)日：1984-06-19
申请号：US302902
申请日：1981-09-16
CPC分类号： G06F13/4234 , G06F13/16
摘要： This disclosure relates to a control system for transferring binary words from a memory system. One thirty two bit double word may be loaded into a selected two of four sixteen bit registers. As a first of the two selected registers is read, another thirty two bit word may be loaded into the unselected registers. Alternatively, sixteen bit single words may be loaded into and read from the registers. When a word has procedural information, it is read from the registers onto a CPU control bus via a multiplexer. When a word is an encoded computer instruction to the CPU, it is read from the registers into a logic unit via a multiplexer. A decoded instruction from the logic unit is read onto a CPU control bus.
摘要翻译： 本公开涉及一种用于从存储器系统传送二进制字的控制系统。 一个三十二位双字可能被加载到四个16位寄存器中选定的两个。 由于读取了两个选定的寄存器中的第一个，可以将另外三十二位的位加载到未选择的寄存器中。 或者，可以将16位单个字加载到寄存器中并从寄存器读取。 当一个单词具有程序信息时，它通过多路复用器从寄存器读取到CPU控制总线上。 当一个字为CPU的编码计算机指令时，它通过多路复用器从寄存器读入逻辑单元。 来自逻辑单元的解码指令被读取到CPU控制总线上。
-
公开(公告)号：US4424561A
公开(公告)日：1984-01-03
申请号：US221854
申请日：1980-12-31
CPC分类号： G06F12/0851
摘要： A cache memory for use in a data processing system wherein data words identified by even address numbers are stored separately from data words associated with odd address numbers to enable the simultaneous transfer of two successively addressed data words to or from the cache memory by the transferring of a data word associated with an odd address number and a data word associated with an even address number.
摘要翻译： 一种在数据处理系统中使用的高速缓存存储器，其中由偶数地址号码识别的数据字与与奇数地址号码相关联的数据字分开存储，以使得能够通过传送 与奇数地址号码相关联的数据字和与偶数地址号码相关联的数据字。
-
公开(公告)号：US4360869A
公开(公告)日：1982-11-23
申请号：US140639
申请日：1980-04-15
CPC分类号： G06F9/226
摘要： A control store included in a data processing system for storing microinstructions in a plurality of microinstructions storage locations is organized in two parts, an upper bank and a lower bank. The lower bank is directly addressed by a portion of the currently addressed control store word, whereas the upper bank is addressed by use of a multiplexer, with inputs thereto coupled from various logic elements. Apparatus is included to determine which part of the control store will be selected and to allow such determination at a time substantially after the addresses for the first and second parts have been received by the control store. In addition, the elements included in the upper bank are selected to have address propagation time sufficiently faster than the address propagation time of the lower bank to compensate for the additional logic propagation delay introduced by the multiplexer so that the contents of the addressed locations of the upper and lower banks are available for use by the system at substantially the same time.
摘要翻译： 包括在用于存储多个微指令存储位置中的微指令的数据处理系统中的控制存储器被组织在两个部分中，即上部存储体和下部存储体。 低级组由当前寻址的控制存储字的一部分直接寻址，而上部组通过使用多路复用器来寻址，其输入从各种逻辑元件耦合。 包括设备以确定控制存储器的哪个部分将被选择，并且在大多数情况下允许由控制存储器接收到第一和第二部分的地址之后的这种确定。 此外，包括在上层中的元件被选择为具有比下层的地址传播时间足够快的地址传播时间，以补偿由多路复用器引入的附加逻辑传播延迟，使得寻址的位置的内容 大部分同时，系统可以使用上下库。
-
5.发明授权
公开(公告)号：US4206503A
公开(公告)日：1980-06-03
申请号：US868251
申请日：1978-01-10
CPC分类号： G06F9/342
摘要： A final effective address of an operand is generated in a microprogrammed data processing system by use of a base address register which may include an unindexed address, an index register which may include an indexed address value, an instruction register which may include an instruction word, which instruction word provides control over the addressing of a control store dependent upon the state of a selected one of a plurality of test conditions. One of the test conditions indicating whether some of the addressing values used in the generation of the effective address are in a short address format or in a long address format. The address control store word provides signals for controlling the operation of the system, including the branch in between such major operations as instruction fetching, addressing, reading, writing, and execution as well as branching between minor operations which are included in the major operations.
摘要翻译： 操作数的最终有效地址是通过使用可包括无索引地址的基址寄存器，可包括索引地址值的索引寄存器，可包括指令字的指令寄存器，在微程序数据处理系统中生成的， 该指令字取决于多个测试条件中所选择的一个的状态来提供对控制存储器的寻址的控制。 测试条件之一是指示在生成有效地址时使用的一些寻址值是短地址格式还是长地址格式。 地址控制存储字提供用于控制系统的操作的信号，包括在诸如指令获取，寻址，读取，写入和执行等主要操作之间的分支以及主要操作中包括的次要操作之间的分支。
-
公开(公告)号：US4074353A
公开(公告)日：1978-02-14
申请号：US689014
申请日：1976-05-24
CPC分类号： G06F9/462
摘要： A plurality of trap save areas are linked to form a pool of such areas from which an area may be loaded with context from various sources in response to a trap condition, such as the addressing of unuseable memory, the loaded area unlinked from the pool, and various pointers changed to reflect such unlinking. The unlinked area is associated with the process which was executing at the time of the occurrence of the trap condition by effectively being coupled to the interrupt level of such process. Independent of the interrupt level, a trap handler routine, specific to the nature of the trap condition, is executed following which the unlinked area is returned to the pool and the various pointers changed to reflect such return.
-
7.发明授权Microprogrammed control of extended integer and commercial instruction processor instructions through use of a data type field in a central processor unit 失效通过使用中央处理器单元中的数据类型字段对扩展整数和商业指令处理器指令进行微编程控制
公开(公告)号：US4491908A
公开(公告)日：1985-01-01
申请号：US326442
申请日：1981-12-01
CPC分类号： G06F9/30192 , G06F9/26 , G06F9/268
摘要： A data processing system includes a microprogram controlled central processing unit that executes instructions. The instruction words include a data type field for identifying the type of operand processed during the execution of the instruction. The data type field signals and a number of control signals are applied to the address terminals of a read only memory. The read only memory output signals are tested by microwords of a microprogram to branch to firmware routines to process the operand type.
摘要翻译： 数据处理系统包括执行指令的微程序控制的中央处理单元。 指令字包括用于识别在执行指令期间处理的操作数的类型的数据类型字段。 数据类型场信号和多个控制信号被施加到只读存储器的地址端子。 只读存储器输出信号由微程序的微字测试以分支到固件例程以处理操作数类型。
-
8.发明授权
公开(公告)号：US4460959A
公开(公告)日：1984-07-17
申请号：US302904
申请日：1981-09-16
CPC分类号： G06F12/0859
摘要： A logic control system comprised of a cache memory system and a transfer control logic unit is disclosed for accommodating the flow of both procedural information and CPU (central processing unit) instructions from a central memory system on a common communication bus to a CPU. The CPU and the transfer control logic unit communicate by way of the cache memory system with the common communication bus. In response to a CPU request to the central memory system, procedural information and instructions are requested by the transfer control logic unit from the cache memory system and presented to the CPU in such a manner as to avoid interruptions in CPU activity caused by information transfer delays.
摘要翻译： 公开了一种由高速缓冲存储器系统和传送控制逻辑单元组成的逻辑控制系统，用于将来自中央存储器系统的程序信息和CPU（中央处理单元）指令的流程从公共通信总线上的CPU接收到CPU。 CPU和传输控制逻辑单元通过具有公共通信总线的高速缓冲存储器系统进行通信。 响应于对中央存储器系统的CPU请求，传输控制逻辑单元从高速缓冲存储器系统请求程序信息和指令，并以这样的方式呈现给CPU，以避免由信息传输延迟引起的CPU活动中断 。
-
9.发明授权Interface for controlling information transfers between main data processing systems units and a central subsystem 失效用于控制主数据处理系统单元和中央子系统之间的信息传输的接口
公开(公告)号：US4371928A
公开(公告)日：1983-02-01
申请号：US140623
申请日：1980-04-15
CPC分类号： G06F12/04 , G06F13/1678
摘要： In a data processing system, a system memory includes first memory modules having a data path of a first bit width and second memory modules having a data path of a second bit width with the first bit width being less than the second bit width. A central subsystem includes a cache memory unit and processing units for initiating requests for data transfers of the second bit width between the system memory and the subsystem processing units. An interface coupling the system memory and the central subsystem for bidirectional data transfers generates, in response to a memory request of a second bit width wherein the requested data is stored in a first memory module, additional memory requests until sufficient data has been retrieved from the system memory to satisfy the central subsystem request. The interface also monitors data transfers between the system processing units and the system memory and transfers the data transfers to the central subsystem in order to update and to retain the integrity of the cache memory in the central subsystem.
摘要翻译： 在数据处理系统中，系统存储器包括具有第一位宽度的数据路径的第一存储器模块和具有第二位宽度的数据路径的第二存储器模块，第一位宽小于第二位宽度。 中央子系统包括高速缓冲存储器单元和处理单元，用于启动系统存储器和子系统处理单元之间的第二位宽的数据传输请求。 耦合系统存储器和用于双向数据传输的中央子系统的接口响应于第二位宽度的存储器请求而产生其中所请求的数据存储在第一存储器模块中的附加存储器请求，直到从 系统内存以满足中央子系统的要求。 该接口还监视系统处理单元和系统存储器之间的数据传输，并将数据传输传送到中央子系统，以便更新并保持高速缓冲存储器在中央子系统中的完整性。
-
公开(公告)号：US4348723A
公开(公告)日：1982-09-07
申请号：US140642
申请日：1980-04-15
CPC分类号： G06F9/267
摘要： A first bank or a second bank of storage locations of a control store of a data processing system is enabled in response to one of a plurality of test signals received as parallel inputs by two multiplexer devices. Only one of the multiplexers is enabled at a given time in response to the polarity of one of the test signals selected from the inputs of the multiplexer devices.
摘要翻译： 响应于由两个多路复用器装置作为并行输入接收的多个测试信号中的一个启用数据处理系统的控制存储器的第一存储体或第二存储区域。 响应于从多路复用器装置的输入中选择的一个测试信号的极性，在给定时间只有一个复用器被使能。
-
-
-
-
-
-
-
-
-
搜索结果
26 条记录 (耗时 0.026 秒)
