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公开(公告)号：US4467417A
公开(公告)日：1984-08-21
申请号：US302903
申请日：1981-09-16
CPC分类号： G06F9/30181 , G06F9/3016 , G06F9/325
摘要： A logic control system is disclosed for accommodating the flow of both procedural information and CPU (central processing unit) instructions from a central memory system to a CPU without compromising memory bandwidths or CPU execution speeds because of transfer delays or timing variances. Instruction modifications and plural task assignments are accommodated during instruction execution.
摘要翻译： 公开了一种逻辑控制系统，用于将过程信息和CPU（中央处理单元）指令的流程从中央存储器系统适应到CPU，而不会因为传输延迟或定时方差而危及存储器带宽或CPU执行速度。 在指令执行期间容纳指令修改和多任务分配。
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2.发明授权
公开(公告)号：US4349874A
公开(公告)日：1982-09-14
申请号：US140630
申请日：1980-04-15
CPC分类号： G06F12/0862 , G06F2212/6022
摘要： In a data processing system, a central processor unit requests procedural data words or non-procedural data words stored in the system memory. A control store device executes firmware instructions including a local bus field for controlling the transfer of the requested procedural data words and non-procedural data words to the central processor unit. The requested procedural data words and non-procedural data words are transferred to the central processing unit by an interfacing device including a data bus latch for receiving the procedural data words and non-procedural data words transferred from the memory, a prefetch buffer for storing up to four words, a first set of OR gate circuits for selectively transferring the procedural data words stored in the prefetch buffer to a procedural data multiplexer for assembling either a procedural data word or a procedure address, and a second set of OR gate circuits for selectively transferring either a procedural data word or non-procedural data word to the source bus or a procedural data address or non-procedural data address to the source bus for transfer to the central processor unit.
摘要翻译： 在数据处理系统中，中央处理器单元请求存储在系统存储器中的过程数据字或非程序数据字。 控制存储设备执行固件指令，其包括本地总线字段，用于控制所请求的过程数据字和非程序数据字向中央处理器单元的传送。 所请求的程序数据字和非程序数据字通过包括用于接收程序数据字的数据总线锁存器和从存储器传送的非程序数据字的接口装置传送到中央处理器，用于存储的预取缓冲器 四个字，第一组OR门电路，用于选择性地将存储在预取缓冲器中的程序数据字传送到程序数据多路复用器，用于组装程序数据字或程序地址，以及第二组OR门电路，用于选择性地 将程序数据字或非程序数据字传送到源总线或程序数据地址或非程序数据地址到源总线以传送到中央处理器单元。
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3.发明授权
公开(公告)号：US4348724A
公开(公告)日：1982-09-07
申请号：US140643
申请日：1980-04-15
CPC分类号： G06F9/265
摘要： A data processing system includes a first memory for storing microinstructions in a first plurality of storage locations and second memory for storing microinstructions in a second plurality of storage locations. A central processor executing a series of addressed microinstructions to control the functions performed by this system generates the address of the next microinstruction to be executed in series as well as a next address selection signal. Addressing circuitry concurrently applies the next address generated by the processor to address inputs of each of the first memory and the second memory. After a predetermined delay, either the first memory or the second memory is selected to output an address microinstruction responsive to the value of the next address selection signal.
摘要翻译： 数据处理系统包括用于存储第一多个存储位置中的微指令的第一存储器和用于在第二多个存储位置中存储微指令的第二存储器。 执行一系列寻址微指令以控制由该系统执行的功能的中央处理器产生要串行执行的下一个微指令的地址以及下一个地址选择信号。 寻址电路同时将由处理器产生的下一个地址应用于地址第一存储器和第二存储器中的每一个的输入。 在预定的延迟之后，选择第一存储器或第二存储器以响应于下一个地址选择信号的值来输出地址微指令。
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公开(公告)号：US4451883A
公开(公告)日：1984-05-29
申请号：US326260
申请日：1981-12-01
CPC分类号： G06F9/30032 , G06F9/30167
摘要： A data processing system includes a memory subsystem for storing operands and instructions and a central processing unit (CPU) for manipulating the operands by executing the instructions. The CPU includes a control store for generating signals for controlling the CPU operation. Shifters made up of multiplexers shift operands between an outer bus and a write bus in response to control store signals. The multiplexers shift the operands left or right 1, 2 or 4-bit positions including open shifts and circular shifts and also perform byte position shifting and twinning.
摘要翻译： 数据处理系统包括用于存储操作数和指令的存储器子系统和用于通过执行指令来操纵操作数的中央处理单元（CPU）。 CPU包括用于产生用于控制CPU操作的信号的控制存储器。 由复用器组成的移位器响应于控制存储信号在外部总线和写入总线之间移动操作数。 多路复用器将操作数向左或向右移位1,2或4位位置，包括开位移和循环移位，并且还执行字节位移和孪生。
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公开(公告)号：US4438493A
公开(公告)日：1984-03-20
申请号：US280720
申请日：1981-07-06
摘要： A technique and apparatus for storing data and addressing stored data in a memory from which multiple words of data are to be retrieved in parallel is disclosed. The memory is addressed by providing the address of the first of N consecutive words to be retrieved in parallel. The data is stored in memory in physical data words which contain N logical data words such that the addressing of one physical data word will result in N logical data words being read in parallel from the memory. Each physical data word contains the contents of the logical data word having the same address as that of the physical data word in its leftmost position followed in the next right position by the contents of the logical data word having the next higher address, and so on until the rightmost position of the physical data word contains the contents of the logical data word with an address equal to the physical data word address plus N-1. This results in the contents of each logical data word being stored N times in the memory, but eliminates the need for data alignment as the N logical data words are read in parallel from the memory.
摘要翻译： 公开了一种用于存储数据并将存储的数据寻址到并行地检索多个数据字的存储器中的技术和装置。 通过提供并行检索的N个连续字中的第一个字的地址来寻址存储器。 将数据存储在存储有包含N个逻辑数据字的物理数据字中，使得一个物理数据字的寻址将导致从存储器并行读取的N个逻辑数据字。 每个物理数据字包含具有与其最左侧位置的物理数据字的地址相同的地址的逻辑数据字的内容，紧接在下一个右侧位置，具有具有下一个较高地址的逻辑数据字的内容，等等 直到物理数据字的最右边位置包含地址等于物理数据字地址加N-1的逻辑数据字的内容。 这导致每个逻辑数据字的内容在存储器中被存储N次，但是当N个逻辑数据字从存储器并行读取时，不需要数据对准。
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6.发明授权
公开(公告)号：US4460959A
公开(公告)日：1984-07-17
申请号：US302904
申请日：1981-09-16
CPC分类号： G06F12/0859
摘要： A logic control system comprised of a cache memory system and a transfer control logic unit is disclosed for accommodating the flow of both procedural information and CPU (central processing unit) instructions from a central memory system on a common communication bus to a CPU. The CPU and the transfer control logic unit communicate by way of the cache memory system with the common communication bus. In response to a CPU request to the central memory system, procedural information and instructions are requested by the transfer control logic unit from the cache memory system and presented to the CPU in such a manner as to avoid interruptions in CPU activity caused by information transfer delays.
摘要翻译： 公开了一种由高速缓冲存储器系统和传送控制逻辑单元组成的逻辑控制系统，用于将来自中央存储器系统的程序信息和CPU（中央处理单元）指令的流程从公共通信总线上的CPU接收到CPU。 CPU和传输控制逻辑单元通过具有公共通信总线的高速缓冲存储器系统进行通信。 响应于对中央存储器系统的CPU请求，传输控制逻辑单元从高速缓冲存储器系统请求程序信息和指令，并以这样的方式呈现给CPU，以避免由信息传输延迟引起的CPU活动中断 。
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公开(公告)号：US4348723A
公开(公告)日：1982-09-07
申请号：US140642
申请日：1980-04-15
CPC分类号： G06F9/267
摘要： A first bank or a second bank of storage locations of a control store of a data processing system is enabled in response to one of a plurality of test signals received as parallel inputs by two multiplexer devices. Only one of the multiplexers is enabled at a given time in response to the polarity of one of the test signals selected from the inputs of the multiplexer devices.
摘要翻译： 响应于由两个多路复用器装置作为并行输入接收的多个测试信号中的一个启用数据处理系统的控制存储器的第一存储体或第二存储区域。 响应于从多路复用器装置的输入中选择的一个测试信号的极性，在给定时间只有一个复用器被使能。
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公开(公告)号：US4467416A
公开(公告)日：1984-08-21
申请号：US302898
申请日：1981-09-16
CPC分类号： G06F9/325 , G06F9/3016
摘要： A logic control system is disclosed for accommodating the flow of both procedural information and CPU (central processing unit) instructions from a central memory system to a CPU without compromising memory bandwidths or CPU execution speeds because of transfer delays or timing variances. Instruction modifications and plural task assignments are accommodated during instruction execution.
摘要翻译： 公开了一种逻辑控制系统，用于将过程信息和CPU（中央处理单元）指令的流程从中央存储器系统适应到CPU，而不会因为传输延迟或定时方差而危及存储器带宽或CPU执行速度。 在指令执行期间容纳指令修改和多任务分配。
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公开(公告)号：US4455606A
公开(公告)日：1984-06-19
申请号：US302902
申请日：1981-09-16
CPC分类号： G06F13/4234 , G06F13/16
摘要： This disclosure relates to a control system for transferring binary words from a memory system. One thirty two bit double word may be loaded into a selected two of four sixteen bit registers. As a first of the two selected registers is read, another thirty two bit word may be loaded into the unselected registers. Alternatively, sixteen bit single words may be loaded into and read from the registers. When a word has procedural information, it is read from the registers onto a CPU control bus via a multiplexer. When a word is an encoded computer instruction to the CPU, it is read from the registers into a logic unit via a multiplexer. A decoded instruction from the logic unit is read onto a CPU control bus.
摘要翻译： 本公开涉及一种用于从存储器系统传送二进制字的控制系统。 一个三十二位双字可能被加载到四个16位寄存器中选定的两个。 由于读取了两个选定的寄存器中的第一个，可以将另外三十二位的位加载到未选择的寄存器中。 或者，可以将16位单个字加载到寄存器中并从寄存器读取。 当一个单词具有程序信息时，它通过多路复用器从寄存器读取到CPU控制总线上。 当一个字为CPU的编码计算机指令时，它通过多路复用器从寄存器读入逻辑单元。 来自逻辑单元的解码指令被读取到CPU控制总线上。
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公开(公告)号：US4360869A
公开(公告)日：1982-11-23
申请号：US140639
申请日：1980-04-15
CPC分类号： G06F9/226
摘要： A control store included in a data processing system for storing microinstructions in a plurality of microinstructions storage locations is organized in two parts, an upper bank and a lower bank. The lower bank is directly addressed by a portion of the currently addressed control store word, whereas the upper bank is addressed by use of a multiplexer, with inputs thereto coupled from various logic elements. Apparatus is included to determine which part of the control store will be selected and to allow such determination at a time substantially after the addresses for the first and second parts have been received by the control store. In addition, the elements included in the upper bank are selected to have address propagation time sufficiently faster than the address propagation time of the lower bank to compensate for the additional logic propagation delay introduced by the multiplexer so that the contents of the addressed locations of the upper and lower banks are available for use by the system at substantially the same time.
摘要翻译： 包括在用于存储多个微指令存储位置中的微指令的数据处理系统中的控制存储器被组织在两个部分中，即上部存储体和下部存储体。 低级组由当前寻址的控制存储字的一部分直接寻址，而上部组通过使用多路复用器来寻址，其输入从各种逻辑元件耦合。 包括设备以确定控制存储器的哪个部分将被选择，并且在大多数情况下允许由控制存储器接收到第一和第二部分的地址之后的这种确定。 此外，包括在上层中的元件被选择为具有比下层的地址传播时间足够快的地址传播时间，以补偿由多路复用器引入的附加逻辑传播延迟，使得寻址的位置的内容 大部分同时，系统可以使用上下库。
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