公开(公告)号：US07019326B2

公开(公告)日：2006-03-28

申请号：US10714139

申请日：2003-11-14

申请人： Stephen M. Cea ,  Ravindra Soman ,  Ramune Nagisetty ,  Sunit Tyagi ,  Sanjay Natarajan

发明人： Stephen M. Cea ,  Ravindra Soman ,  Ramune Nagisetty ,  Sunit Tyagi ,  Sanjay Natarajan

IPC分类号： H01L29/06

CPC分类号： H01L29/66636 ,  H01L29/1054 ,  H01L29/7842

摘要： Various methods for forming a layer of strained silicon in a channel region of a device and devices constructed according to the disclosed methods. In one embodiment, a strain-inducing layer is formed, a relaxed layer is formed on the strain-inducing layer, a portion of the strain-inducing layer is removed, which allows the strain-inducing layer to relax and strain the relaxed layer.

公开(公告)号：US06458667B1

公开(公告)日：2002-10-01

申请号：US09531805

申请日：2000-03-21

申请人： Sunit Tyagi ,  Shahriar S. Ahmed

发明人： Sunit Tyagi ,  Shahriar S. Ahmed

IPC分类号： H01L21336

CPC分类号： H01L29/7393

摘要： An improved MOS transistor and method for making it are described. The MOS transistor's source and drain have a first conductivity type and are separated from each other by a first region having a second conductivity type opposite to the first conductivity type. A second region, also having the second conductivity type, is formed adjacent to the drain and is separated from the first region by the drain.

摘要翻译： 描述了一种改进的MOS晶体管及其制造方法。 MOS晶体管的源极和漏极具有第一导电类型，并且通过具有与第一导电类型相反的第二导电类型的第一区域彼此分离。 还具有第二导电类型的第二区域邻近漏极形成，并且通过漏极与第一区域分离。

公开(公告)号：US06297104B1

公开(公告)日：2001-10-02

申请号：US09496833

申请日：2000-02-02

申请人： Sunit Tyagi ,  Shahriar S. Ahmed

发明人： Sunit Tyagi ,  Shahriar S. Ahmed

IPC分类号： H01L21336

CPC分类号： H01L29/6659 ,  H01L29/66659 ,  H01L29/7835

摘要： Metal Oxide Semiconductor Field Effect Transistors (MOSFET) are disclosed. One MOSFET includes, a substrate having a well of a first conductivity type. The MOSFET also includes source and drain regions, of a second conductivity type, formed in the well arranged apart from each other. Moreover, the MOSFET includes a first region, of a second conductivity type, formed in the well near the drain region. The first region has a low doping. Furthermore, the MOSFET includes a second region of a second conductivity type, formed near the source region. The second region has a doping substantially higher than the doping of the first region. A second MOSFET includes a substrate having a well of a first conductivity type and source and drain regions, of a second conductivity type, formed in the well apart from each other. Moreover, the MOSFET includes a drain extension region of the second conductivity type, formed in the well near the drain region. Furthermore, the MOSFET includes a source extension region, of the second conductivity type, formed in the well near the source region. The source extension region is doped more heavily than the drain extension region. The source extension region extends deeper in the well than the drain extension region.

摘要翻译： 公开了金属氧化物半导体场效应晶体管（MOSFET）。 一个MOSFET包括具有第一导电类型的阱的衬底。 MOSFET还包括第二导电类型的源极和漏极区域，其形成在彼此分开布置的阱中。 此外，MOSFET包括形成在漏区附近的阱中的第二导电类型的第一区域。 第一个区域掺杂低。 此外，MOSFET包括在源极区附近形成的第二导电类型的第二区域。 第二区域具有比第一区域的掺杂显着更高的掺杂。 第二MOSFET包括具有第一导电类型的阱以及形成在彼此远离的第二导电类型的源极和漏极区的衬底。 此外，MOSFET包括形成在漏极区附近的阱中的第二导电类型的漏极延伸区域。 此外，MOSFET包括形成在源区附近的阱中的第二导电类型的源极延伸区域。 源极延伸区域比漏极延伸区域更重掺杂。 源极延伸区域在阱中比漏极延伸区域更深。

公开(公告)号：US06200879B1

公开(公告)日：2001-03-13

申请号：US09210271

申请日：1998-12-10

申请人： Sunit Tyagi

发明人： Sunit Tyagi

IPC分类号： H01L2176

CPC分类号： H01L21/76237 ,  H01L21/823892

摘要： The present invention is a semiconductor device having and a method for forming wells by growing an epitaxial silicon layer wherein the epitaxial silicon layer has at least three silicon sublayers. The first sublayer is highly doped, the second sublayer is less doped, and the third sublayer is also highly doped. The use of the epitaxially grown wells allows for the placement of high dopant concentrations in regions of the well where electrical isolation is an issue and the placement of lower doped concentrations in regions of the well where electrical isolation is not as great an issue in order to help reduce the problem of parasitic capacitance.

摘要翻译： 本发明是具有通过生长外延硅层形成阱的方法的半导体器件，其中外延硅层具有至少三个硅子层。 第一子层是高掺杂的，第二子层较少掺杂，第三子层也是高度掺杂的。 使用外延生长的孔允许在阱的区域中放置高掺杂剂浓度，其中电隔离是问题，并且在阱的区域中放置较低的掺杂浓度，其中电绝缘不是很大的问题，以便 有助于减少寄生电容的问题。

公开(公告)号：US20120019072A1

公开(公告)日：2012-01-26

申请号：US12840130

申请日：2010-07-20

申请人： Sunit Tyagi ,  Hemanshu Bhatt

发明人： Sunit Tyagi ,  Hemanshu Bhatt

IPC分类号： H02J1/10

CPC分类号： H02M7/537 ,  H02J3/383 ,  H02M7/493 ,  H02M2007/4815 ,  Y02B70/1441 ,  Y02E10/563 ,  Y10T307/50 ,  Y10T307/658 ,  Y10T307/713

摘要： Embodiments related to the conversion of DC power to AC power are disclosed. For example, one disclosed embodiment provides a power conversion system, comprising a plurality of direct current (DC) power sources, a plurality of power output circuits connected to one another in a parallel arrangement, each power output circuit being connected to a corresponding DC power source to receive power from the corresponding DC power source and to selectively discharge power received from the corresponding DC power source, a power combiner configured to combine power received from the plurality of power output circuits to form a combined power signal, an output stage configured to convert the combined power signal into an AC signal or a DC signal, and a controller in electrical communication with each power outlet circuit and the power combiner to control the output of power by the power converter.

摘要翻译： 公开了将直流电转换为交流电力的实施例。 例如，一个公开的实施例提供了一种功率转换系统，其包括多个直流（DC）电源，多个以并联装置彼此连接的功率输出电路，每个功率输出电路连接到相应的直流电力 源极，用于从相应的直流电源接收电力并选择性地放电从相应的直流电源接收的功率;功率组合器，被配置为组合从多个功率输出电路接收的功率以形成组合的功率信号;输出级，被配置为 将组合的功率信号转换为AC信号或DC信号，以及与每个电源插座电路和功率组合器电连接的控制器，以通过功率转换器来控制功率的输出。

公开(公告)号：US07581154B2

公开(公告)日：2009-08-25

申请号：US11174003

申请日：2005-06-30

申请人： Nivruti Rai ,  Anshumali Kumar ,  Edward Burton ,  Sunit Tyagi ,  Jeffrey L. Miller

发明人： Nivruti Rai ,  Anshumali Kumar ,  Edward Burton ,  Sunit Tyagi ,  Jeffrey L. Miller

IPC分类号： G11C29/00

CPC分类号： G11C11/417

摘要： A method comprising running an error correction code on data and storing the data and the result of the error correction code in memory, running an error correction code on the data when it is read from the memory, comparing the results of the error correction codes on the data from before and after the memory, correcting errors when the comparator determines a difference in the results of the error correction codes and lowering the operating voltage of the memory array while using the error correction.

摘要翻译： 一种方法，包括在数据上运行纠错码并将数据和纠错码的结果存储在存储器中，当从存储器读取数据时对数据进行纠错码，将纠错码的结果与 来自存储器之前和之后的数据，当比较器确定误差校正码的结果的差异并且在使用纠错时降低存储器阵列的工作电压时校正错误。

公开(公告)号：US06787440B2

公开(公告)日：2004-09-07

申请号：US10315268

申请日：2002-12-10

申请人： Christopher G. Parker ,  Markus Kuhn ,  Ying Zhou ,  Scott A. Hareland ,  Suman Datta ,  Nick Lindert ,  Robert S. Chau ,  Timothy E. Glassman ,  Matthew V. Metz ,  Sunit Tyagi

发明人： Christopher G. Parker ,  Markus Kuhn ,  Ying Zhou ,  Scott A. Hareland ,  Suman Datta ,  Nick Lindert ,  Robert S. Chau ,  Timothy E. Glassman ,  Matthew V. Metz ,  Sunit Tyagi

IPC分类号： H01L214763

CPC分类号： H01L21/28194 ,  H01L21/28202 ,  H01L29/513 ,  H01L29/518

摘要： A method for making a semiconductor device is described. That method comprises forming on a substrate a buffer layer and a high-k gate dielectric layer, oxidizing the surface of the high-k gate dielectric layer, and then forming a gate electrode on the oxidized high-k gate dielectric layer.

公开(公告)号：US06372583B1

公开(公告)日：2002-04-16

申请号：US09500556

申请日：2000-02-09

申请人： Sunit Tyagi

发明人： Sunit Tyagi

IPC分类号： H01L21336

CPC分类号： H01L29/0847 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834

摘要： A method for making a semiconductor device. In that method, source and drain regions are epitaxially grown on a first part of a substrate. After a gate oxide is formed on a second part of the substrate, an etched polysilicon layer is formed on the gate oxide.

摘要翻译： 一种制造半导体器件的方法。 在该方法中，源极和漏极区域在衬底的第一部分上外延生长。 在基板的第二部分上形成栅极氧化物之后，在栅极氧化物上形成蚀刻的多晶硅层。

公开(公告)号：US20190265387A1

公开(公告)日：2019-08-29

申请号：US16409055

申请日：2019-05-10

申请人： Sunit Tyagi

发明人： Sunit Tyagi

IPC分类号： G01W1/06 ,  G01W1/17 ,  E02B1/00 ,  F03G7/05 ,  F03D9/30 ,  G06N7/00 ,  F03B17/06

摘要： Surface modification control stations and methods in a globally distributed array for dynamically adjusting the atmospheric, terrestrial and oceanic properties. The control stations modify the humidity, currents, wind flows and heat removal rate of the surface and facilitate cooling and control of large area of global surface temperatures. This global system is made of arrays of multiple sub-systems that monitor climate and act locally on weather with dynamically generated local forcing & perturbations for guiding in a controlled manner aim at long-term modifications. The machineries are part of a large-scale system consisting of an array of many such machines put across the globe at locations called the control stations. These are then used in a coordinated manner to modify large area weather and the global climate as desired. The energy system installed at a control stations, with multiple machines to change the local parameters of the ocean, these stations are powered using renewable energy (RE) sources including Solar, Ocean Currents, Wind, Waves and Batteries to store energy and provide sufficient power and energy as required and available at all hours. This energy is then used to do directed work using special machines, that can be pumps for seawater to move ocean water either amplifying or changing the currents in various locations and at different depths, in addition it will have machineries for changing the vertical depth profile of the ocean of temperature, salinity and currents. Control stations will also directly use devices such as heat pumps to change the temperatures of local water either at surface or at controlled depths, or modify the humidity and salinity to change the atmospheric and oceanic properties as desired. The system will work in a globally coordinated manner applying artificial intelligence and machine learning algorithms to learn from observations to improve the control characteristics and aim to slow down the rise of global surface temperatures. These systems are used to reduce the temperatures of coral reefs, arctic glaciers and south pacific to control the El Nino oscillations.

公开(公告)号：US20080036005A1

公开(公告)日：2008-02-14

申请号：US11874129

申请日：2007-10-17

申请人： Mark Armstrong ,  Gerhard Schrom ,  Sunit Tyagi ,  Paul Packan ,  Kelin Kuhn ,  Scott Thompson

发明人： Mark Armstrong ,  Gerhard Schrom ,  Sunit Tyagi ,  Paul Packan ,  Kelin Kuhn ,  Scott Thompson

IPC分类号： H01L29/76

CPC分类号： H01L27/1446 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/0922 ,  H01L29/045 ,  H01L29/7843 ,  H01L29/7846

摘要： Complementary metal oxide semiconductor transistors are formed on a silicon substrate. The substrate has a {100} crystallographic orientation. The transistors are formed on the substrate so that current flows in the channels of the transistors are parallel to the direction. Additionally, longitudinal tensile stress is applied to the channels.

摘要翻译： 互补金属氧化物半导体晶体管形成在硅衬底上。 基板具有{100}晶体取向。 晶体管形成在衬底上，使得电流在晶体管的沟道中流动平行于<100>方向。 此外，纵向拉伸应力施加到通道。