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    Nitrogen controlled growth of dislocation loop in stress enhanced transistor
    5.
    发明申请
    Nitrogen controlled growth of dislocation loop in stress enhanced transistor 失效
    应力增强晶体管中位错环的氮控制生长

    公开(公告)号：US20050014351A1

    公开(公告)日：2005-01-20

    申请号：US10918818

    申请日：2004-08-12

    申请人： Cory Weber ,  Mark Armstrong ,  Harold Kennel ,  Tahir Ghani ,  Paul Packan ,  Scott Thompson

    发明人： Cory Weber ,  Mark Armstrong ,  Harold Kennel ,  Tahir Ghani ,  Paul Packan ,  Scott Thompson

    IPC分类号： H01L21/265 ,  H01L21/8238 ,  H01L29/78 ,  H01L21/425

    CPC分类号： H01L21/26506 ,  H01L21/823807 ,  H01L29/7833 ,  H01L29/7842

    摘要： Known techniques to improve metal-oxide-semiconductor field effect transistor (MOSFET) performance is to add a high stress dielectric layer to the MOSFET. The high stress dielectric layer introduces stress in the MOSFET that causes electron mobility drive current to increase. This technique increases process complexity, however, and can degrade PMOS performance. Embodiments of the present invention create dislocation loops in the MOSFET substrate to introduce stress and implants nitrogen in the substrate to control the growth of the dislocation loops so that the stress remains beneath the channel of the MOSFET.

    摘要翻译： 改进金属氧化物半导体场效应晶体管（MOSFET）性能的已知技术是向MOSFET增加高应力电介质层。 高应力电介质层在MOSFET中引入应力，导致电子迁移率驱动电流增加。 然而，这种技术提高了工艺复杂度，并且可能降低PMOS性能。 本发明的实施例在MOSFET衬底中产生位错环以在衬底中引入应力和注入氮以控制位错环的生长，使得应力保持在MOSFET的沟道下方。

    LEAKAGE REDUCTION STRUCTURES FOR NANOWIRE TRANSISTORS
    6.
    发明申请
    LEAKAGE REDUCTION STRUCTURES FOR NANOWIRE TRANSISTORS 有权
    纳米晶体管的漏电减少结构

    公开(公告)号：US20140264253A1

    公开(公告)日：2014-09-18

    申请号：US13996845

    申请日：2013-03-14

    申请人： Seiyon Kim ,  Kelin Kuhn ,  Rafael Rios ,  Mark Armstrong

    发明人： Seiyon Kim ,  Kelin Kuhn ,  Rafael Rios ,  Mark Armstrong

    IPC分类号： H01L29/06 ,  H01L29/66 ,  H01L29/786 ,  H01L21/266 ,  H01L29/10 ,  H01L21/265

    CPC分类号： H01L29/0673 ,  H01L29/16 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696

    摘要： A nanowire device of the present description may include a highly doped underlayer formed between at least one nanowire transistor and the microelectronic substrate on which the nanowire transistors are formed, wherein the highly doped underlayer may reduce or substantially eliminate leakage and high gate capacitance which can occur at a bottom portion of a gate structure of the nanowire transistors. As the formation of the highly doped underlayer may result in gate inducted drain leakage at an interface between source structures and drain structures of the nanowire transistors, a thin layer of undoped or low doped material may be formed between the highly doped underlayer and the nanowire transistors.

    摘要翻译： 本描述的纳米线器件可以包括形成在至少一个纳米线晶体管和其上形成纳米线晶体管的微电子衬底之间的高度掺杂的底层，其中高度掺杂的底层可以减少或基本上消除可能发生的泄漏和高栅极电容 在纳米线晶体管的栅极结构的底部。 由于高掺杂底层的形成可能导致在纳米线晶体管的源极结构和漏极结构之间的界面处的栅极感应漏极泄漏，可以在高掺杂底层和纳米线晶体管之间形成未掺杂或低掺杂材料的薄层 。

    Nitrogen controlled growth of dislocation loop in stress enhanced transistor
    7.
    发明授权
    Nitrogen controlled growth of dislocation loop in stress enhanced transistor 有权
    应力增强晶体管中位错环的氮控制生长

    公开(公告)号：US07226824B2

    公开(公告)日：2007-06-05

    申请号：US10918818

    申请日：2004-08-13

    申请人： Cory E. Weber ,  Mark Armstrong ,  Harold Kennel ,  Tahir Ghani ,  Paul A. Packan ,  Scott Thompson

    发明人： Cory E. Weber ,  Mark Armstrong ,  Harold Kennel ,  Tahir Ghani ,  Paul A. Packan ,  Scott Thompson

    IPC分类号： H01L21/338

    CPC分类号： H01L29/7842 ,  H01L21/26506 ,  H01L21/823807 ,  H01L29/7833

    摘要： Known techniques to improve metal-oxide-semiconductor field effect transistor (MOSFET) performance is to add a high stress dielectric layer to the MOSFET. The high stress dielectric layer introduces stress in the MOSFET that causes electron mobility drive current to increase. This technique increases process complexity, however, and can degrade PMOS performance. Embodiments of the present invention create dislocation loops in the MOSFET substrate to introduce stress and implants nitrogen in the substrate to control the growth of the dislocation loops so that the stress remains beneath the channel of the MOSFET.

    摘要翻译： 改进金属氧化物半导体场效应晶体管（MOSFET）性能的已知技术是向MOSFET增加高应力电介质层。 高应力电介质层在MOSFET中引入应力，导致电子迁移率驱动电流增加。 然而，这种技术提高了工艺复杂度，并且可能降低PMOS性能。 本发明的实施例在MOSFET衬底中产生位错环以在衬底中引入应力和注入氮以控制位错环的生长，使得应力保持在MOSFET的沟道下方。

    Nitrogen controlled growth of dislocation loop in stress enhanced transistor
    9.
    发明授权
    Nitrogen controlled growth of dislocation loop in stress enhanced transistor 有权
    应力增强晶体管中位错环的氮控制生长

    公开(公告)号：US06800887B1

    公开(公告)日：2004-10-05

    申请号：US10405110

    申请日：2003-03-31

    申请人： Cory E. Weber ,  Mark Armstrong ,  Harold Kennel ,  Tahir Ghani ,  Paul A. Packan ,  Scott Thompson

    发明人： Cory E. Weber ,  Mark Armstrong ,  Harold Kennel ,  Tahir Ghani ,  Paul A. Packan ,  Scott Thompson

    IPC分类号： H01L2980

    CPC分类号： H01L29/7842 ,  H01L21/26506 ,  H01L21/823807 ,  H01L29/7833

    摘要： Known techniques to improve metal-oxide-semiconductor field effect transistor (MOSFET) performance is to add a high stress dielectric layer to the MOSFET. The high stress dielectric layer introduces stress in the MOSFET that causes electron mobility drive current to increase. This technique increases process complexity, however, and can degrade PMOS performance. Embodiments of the present invention create dislocation loops in the MOSFET substrate to introduce stress and implants nitrogen in the substrate to control the growth of the dislocation loops so that the stress remains beneath the channel of the MOSFET.

    摘要翻译： 改进金属氧化物半导体场效应晶体管（MOSFET）性能的已知技术是向MOSFET增加高应力电介质层。 高应力电介质层在MOSFET中引入应力，导致电子迁移率驱动电流增加。 然而，这种技术提高了工艺复杂度，并且可能降低PMOS性能。 本发明的实施例在MOSFET衬底中产生位错环以在衬底中引入应力和注入氮以控制位错环的生长，使得应力保持在MOSFET的沟道下方。

    Online Booking System
    10.
    发明申请
    Online Booking System 审中-公开
    网上预订系统

    公开(公告)号：US20140095217A1

    公开(公告)日：2014-04-03

    申请号：US13631233

    申请日：2012-09-28

    申请人： Mark Armstrong ,  Stefano Grossi ,  Ken Sauter

    发明人： Mark Armstrong ,  Stefano Grossi ,  Ken Sauter

    IPC分类号： G06Q10/02

    CPC分类号： G06Q10/02

    摘要： An online booking system includes a computer connected to a wide-area network, the computer including a processor and a memory configured to store programming and data. An act database includes entertainment records associated with a plurality of entertainers. Programming causes the processor to receive a performance request from a talent buyer over the network, the performance request including performance request data regarding an open performance date desired to be booked. The system determines if the performance request data matches a respective entertainment record in the act database and, if so, notifies a respective entertainer associated with the selected act to contact the buyer. If the act is booked, the processor updates the act and talent buyer itinerary databases. Matching a performance request with entertainment records may include determining if an entertainer is available within a predetermined number of days of the performance date and within a predetermined distance.

    摘要翻译： 在线预订系统包括连接到广域网的计算机，所述计算机包括处理器和被配置为存储编程和数据的存储器。 行为数据库包括与多个艺人相关联的娱乐记录。 编程使得处理器通过网络从人才买家接收性能请求，性能请求包括关于期望预定的开放性能日期的性能请求数据。 系统确定性能请求数据是否与动作数据库中的相应娱乐记录相匹配，如果是，则通知与所选择的行为相关联的相应艺人以联系买方。 如果该行为被预订，处理器更新行为和人才买家行程数据库。 将演奏请求与娱乐记录相匹配可以包括在演出日期的预定天数内并且在预定距离内确定艺人是否可用。