公开(公告)号：US20080135891A1

公开(公告)日：2008-06-12

申请号：US11608577

申请日：2006-12-08

申请人： Ana Claudia Arias ,  Rene Lujan ,  Robert Street

发明人： Ana Claudia Arias ,  Rene Lujan ,  Robert Street

IPC分类号： H01L29/76

CPC分类号： H01L29/7869 ,  H01L21/31683 ,  H01L29/4908 ,  H01L51/0097 ,  H01L51/0525 ,  H01L51/055

摘要： A transistor device is formed on a flexible substrate such that device processing remains at a low temperature. A first gate dielectric layer is formed over gate metal by annodization, eliminating relatively high-temperature dielectric deposition processes and difficulties with in-process substrate deformation. A second gate dielectric layer may optionally be provided over the first in order to provide an improved dielectric/semiconductor interface. A high performance pixel, and process for producing same, may thus be provided on a flexible substrate.

摘要翻译： 在柔性基板上形成晶体管器件，使得器件处理保持在低温。 第一栅极电介质层通过再生形成在栅极金属上，消除了相对高温的电介质沉积过程和在过程中基板变形的困难。 可以可选地在第一栅极介质层上提供第二栅极电介质层，以便提供改进的电介质/半导体界面。 因此，可以在柔性基板上提供高性能像素及其制造方法。

公开(公告)号：US20070235410A1

公开(公告)日：2007-10-11

申请号：US11394438

申请日：2006-03-31

申请人： William Wong ,  Scott Limb ,  Beverly Russo ,  Michael Chabinyc ,  Rene Lujan

发明人： William Wong ,  Scott Limb ,  Beverly Russo ,  Michael Chabinyc ,  Rene Lujan

IPC分类号： C23F1/00

CPC分类号： B44C1/22 ,  H01L27/1292 ,  H01L29/4908

摘要： Susceptibility of darkfield etch masks (majority of the mask area is opaque) to pinhole defects, transferred pattern, non-uniformity, etc. due to ejector dropout or drop misdirection, and long duty cycles due to large-area coverage, when using digital lithography (or print patterning) is addressed by using a clear-field print pattern that is then coated with etch resist material. The printed clear field pattern is selectively removed to form an inverse pattern (darkfield) within the coated resist layer. Etching then removes selected portions of an underlying (e.g., encapsulation, conductive, etc.) layer. Removal of the mask produces a layer with large-area features with substantially reduced defects.

摘要翻译： 当使用数字光刻技术时，由于喷射器脱落或滴落错误导向，暗区蚀刻掩模（大部分掩模区域不透明）对针孔缺陷，转印图案，不均匀性等的敏感性以及由于大面积覆盖而造成的长占空比 （或印刷图案化）通过使用随后涂覆有抗蚀剂材料的透明场印刷图案来解决。 选择性地去除打印的清晰场图案以在涂覆的抗蚀剂层内形成反向图案（暗场）。 然后蚀刻去除底层（例如，封装，导电等）层的选定部分。 去除掩模产生具有大面积特征并具有显着减少的缺陷的层。

公开(公告)号：US20070158644A1

公开(公告)日：2007-07-12

申请号：US11316551

申请日：2005-12-21

申请人： Michael Chabinyc ,  Rene Lujan ,  Ana Arias ,  Jackson Ho

发明人： Michael Chabinyc ,  Rene Lujan ,  Ana Arias ,  Jackson Ho

IPC分类号： H01L29/08

CPC分类号： H01L27/283 ,  H01L51/0037 ,  H01L51/0541 ,  H01L51/0545 ,  H01L51/105

摘要： A backplane circuit includes an array of organic thin-film transistors (OTFTs), each OTFT including a source contact, a drain contact, and an organic semiconductor region extending between the source and drain contacts. The drain contacts in each row are connected to an address line. The source and drain contacts and the address lines are fabricated using a multi-layer structure including a relatively thick base portion formed of a relatively inexpensive metal (e.g., aluminum or copper), and a relatively thin contact layer formed of a high work function, low oxidation metal (e.g., gold) that exhibits good electrical contact to the organic semiconductor, is formed opposite at least one external surface of the base, and is located at least partially in an interface region where the organic semiconductor contacts an underlying dielectric layer.

摘要翻译： 背板电路包括有机薄膜晶体管（OTFT）的阵列，每个OTFT包括源极接触，漏极接触以及在源极和漏极接触之间延伸的有机半导体区域。 每行的漏极触点连接到地址线。 源极和漏极触点和地址线使用包括由相对便宜的金属（例如，铝或铜）形成的相对厚的基部的多层结构以及由高功函数形成的相对较薄的接触层制造， 与有机半导体呈现良好的电接触的低氧化金属（例如，金）形成在与基底的至少一个外表面相对的位置，并且至少部分地位于有机半导体与下面的介电层接触的界面区域中。