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    Programmable sequential logic array mechanism
    21.
    发明授权
    Programmable sequential logic array mechanism 失效
    可编程顺序逻辑阵列机制

    公开(公告)号：US4357678A

    公开(公告)日：1982-11-02

    申请号：US106824

    申请日：1979-12-26

    申请人： Gordon T. Davis

    发明人： Gordon T. Davis

    IPC分类号： G06F7/00 ,  G06F9/22 ,  H03K19/173 ,  H03K19/177 ,  H03K19/20

    CPC分类号： G06F9/223 ,  H03K19/1737 ,  H03K19/17712 ,  H03K19/1772

    摘要： A programmable sequential logic array mechanism is provided for performing logical operations and solving logical equations. The mechanism includes a search array subsystem for receiving a plurality of binary input signals. The search array subsystem includes an addressable storage array for supplying input control words for testing for different input signal conditions. The sequential logic array mechanism also includes a read array subsystem for producing a plurality of binary output signals. This read array subsystem includes an addressable storage array for supplying output signal control words. The results of the tests performed by the search array subsystem are used to select which ones of the output signal control words are allowed to establish or change the read array output signals.

    摘要翻译： 提供了一种用于执行逻辑运算和求解逻辑方程的可编程顺序逻辑阵列机制。 该机构包括用于接收多个二进制输入信号的搜索阵列子系统。 搜索阵列子系统包括用于提供用于测试不同输入信号条件的输入控制字的可寻址存储阵列。 顺序逻辑阵列机构还包括用于产生多个二进制输出信号的读阵列子系统。 该读取阵列子系统包括用于提供输出信号控制字的可寻址存储阵列。 搜索阵列子系统执行的测试结果用于选择哪些输出信号控制字被允许建立或改变读数组输出信号。

    Caching lookups based upon TCP traffic flow characteristics
    22.
    发明授权
    Caching lookups based upon TCP traffic flow characteristics 失效
    基于TCP流量特性的缓存查找

    公开(公告)号：US08005989B2

    公开(公告)日：2011-08-23

    申请号：US12188333

    申请日：2008-08-08

    申请人： Everett A. Corl, Jr. ,  Gordon T. Davis ,  Clark D. Jeffries ,  Natarajan Vaidhyanathan ,  Colin B. Verrilli

    发明人： Everett A. Corl, Jr. ,  Gordon T. Davis ,  Clark D. Jeffries ,  Natarajan Vaidhyanathan ,  Colin B. Verrilli

    IPC分类号： G06F15/173

    CPC分类号： H04L45/00 ,  H04L69/22

    摘要： The classification system of a network device includes a cache in which a mapping between predefined characteristics of TCP/IP packets and associated actions are stored in response to the first “Frequent Flyer” packet in of a session. Selected characteristics from subsequent received packets of that session are correlated with the predefined characteristics and the stored actions are applied to the received packets if the selected characteristics and the predefined characteristics match, thus reducing the processing required for subsequent packets. The packets selected for caching may be data packets. For mismatched characteristics, the full packet search of the classification system is used to determine the action to apply to the received packet.

    摘要翻译： 网络设备的分类系统包括缓存，其中响应于会话中的第一“频繁传单”分组而存储TCP / IP分组的预定义特性与相关动作之间的映射。 如果所选择的特征和预定义的特征匹配，则从该会话的后续接收到的分组中选出的特征与预定义的特征相关联，并且将存储的动作应用于所接收的分组，从而减少后续分组所需的处理。 选择用于缓存的数据包可能是数据包。 对于不匹配的特征，分类系统的全分组搜索用于确定应用于接收到的分组的动作。

    Decision tree multi-field classification dynamic rules updating and rebuilding
    23.
    发明授权
    Decision tree multi-field classification dynamic rules updating and rebuilding 失效
    决策树多场分类动态规则更新和重建

    公开(公告)号：US07937355B2

    公开(公告)日：2011-05-03

    申请号：US12327115

    申请日：2008-12-03

    申请人： Everett A. Corl, Jr. ,  Gordon T. Davis ,  Clark D. Jeffries

    发明人： Everett A. Corl, Jr. ,  Gordon T. Davis ,  Clark D. Jeffries

    IPC分类号： G06F17/00 ,  G06F9/00 ,  G06F15/16 ,  G06F15/173 ,  G06N5/02

    CPC分类号： H04L43/16 ,  H04L43/18 ,  H04L49/25 ,  H04L63/0263

    摘要： The present invention relates to a method and computer system device for applying a plurality of rules to data packets within a network computer system. A filter rule decision tree is updated by adding or deleting a rule. If deleting a filter rule then the decision tree is provided to a network data plane processor with an incremental delete of the filter rule. If adding a filter rule then either providing an incremental insertion of the filter rule to the decision tree or rebuilding the first decision tree into a second decision tree responsive to comparing a parameter to a threshold. In one embodiment the parameter and thresholds relate to depth values of the tree filter rule chained branches. In another the parameter and thresholds relate to a total count of rule additions since a building of the relevant tree.

    摘要翻译： 本发明涉及一种用于将多个规则应用于网络计算机系统内的数据分组的方法和计算机系统设备。 通过添加或删除规则来更新过滤规则决策树。 如果删除过滤规则，则将决策树提供给具有过滤规则的增量删除的网络数据平面处理器。 如果添加过滤规则，则响应于将参数与阈值进行比较，提供过滤规则的增量插入到决策树或将第一决策树重新构建到第二决策树中。 在一个实施例中，参数和阈值涉及树筛选器规则链分支的深度值。 在另一个中，参数和阈值涉及自相关树的建立以来的规则添加的总计数。

    Performance of a cache by detecting cache lines that have been reused
    24.
    发明授权
    Performance of a cache by detecting cache lines that have been reused 有权
    通过检测已被重用的高速缓存行来执行缓存的性能

    公开(公告)号：US07552286B2

    公开(公告)日：2009-06-23

    申请号：US12051012

    申请日：2008-03-19

    申请人： Gordon T. Davis ,  Santiago A. Leon ,  Hans-Werner Tast

    发明人： Gordon T. Davis ,  Santiago A. Leon ,  Hans-Werner Tast

    IPC分类号： G06F13/00

    CPC分类号： G06F12/127

    摘要： A method and system for improving the performance of a cache. The cache may include an array of tag entries where each tag entry includes an additional bit (“reused bit”) used to indicate whether its associated cache line has been reused, i.e., has been requested or referenced by the processor. By tracking whether a cache line has been reused, data (cache line) that may not be reused may be replaced with the new incoming cache line prior to replacing data (cache line) that may be reused. By replacing data in the cache memory that might not be reused prior to replacing data that might be reused, the cache hit may be improved thereby improving performance.

    摘要翻译： 一种用于提高缓存性能的方法和系统。 高速缓存可以包括标签条目的阵列，其中每个标签条目包括用于指示其相关联的高速缓存行是否被重用，即被处理器请求或引用的附加位（“重用位”）。 通过跟踪高速缓存行是否被重用，在替换可被重用的数据（高速缓存行）之前，可以用新的传入高速缓存行替换可能不被重用的数据（高速缓存行）。 通过在替换可能被重用的数据之前替换高速缓冲存储器中可能不被重用的数据，可以提高高速缓存命中，从而提高性能。

    STRUCTURE FOR A MEMORY-CENTRIC PAGE TABLE WALKER
    25.
    发明申请
    STRUCTURE FOR A MEMORY-CENTRIC PAGE TABLE WALKER 有权
    一个记忆中央页面表格的结构

    公开(公告)号：US20090158003A1

    公开(公告)日：2009-06-18

    申请号：US12109671

    申请日：2008-04-25

    申请人： Sumedh W. Sathaye ,  Gordon T. Davis

    发明人： Sumedh W. Sathaye ,  Gordon T. Davis

    IPC分类号： G06F9/34

    CPC分类号： G06F12/10 ,  G06F12/0888 ,  G06F12/1027

    摘要： A design structure embodied in a machine readable storage medium for at least one of designing, manufacturing, and testing a design is provided. The design structure includes a page table walker. The page table walker is moved from its conventional location in the memory management unit associated with the data processor to a location in main memory i.e. the main memory controller. As a result, wherein the processing of requests for data could selectively avoid or bypass cumbersome caches associated with the data processor.

    摘要翻译： 提供了一种体现在用于设计，制造和测试设计中的至少一个的机器可读存储介质中的设计结构。 设计结构包括页表步行器。 页表助行器从与数据处理器相关联的存储器管理单元中的常规位置移动到主存储器（即主存储器控制器）中的位置。 结果，其中对数据请求的处理可以选择性地避免或绕过与数据处理器相关联的麻烦的高速缓存。

    PERFORMANCE OF A CACHE BY DETECTING CACHE LINES THAT HAVE BEEN REUSED
    27.
    发明申请
    PERFORMANCE OF A CACHE BY DETECTING CACHE LINES THAT HAVE BEEN REUSED 有权
    通过检测已被重新使用的缓存行，缓存的性能

    公开(公告)号：US20080168236A1

    公开(公告)日：2008-07-10

    申请号：US12051012

    申请日：2008-03-19

    申请人： Gordon T. Davis ,  Santiago A. Leon ,  Hans-Werner Tast

    发明人： Gordon T. Davis ,  Santiago A. Leon ,  Hans-Werner Tast

    IPC分类号： G06F12/08

    CPC分类号： G06F12/127

    摘要： A method and system for improving the performance of a cache. The cache may include an array of tag entries where each tag entry includes an additional bit (“reused bit”) used to indicate whether its associated cache line has been reused, i.e., has been requested or referenced by the processor. By tracking whether a cache line has been reused, data (cache line) that may not be reused may be replaced with the new incoming cache line prior to replacing data (cache line) that may be reused. By replacing data in the cache memory that might not be reused prior to replacing data that might be reused, the cache hit may be improved thereby improving performance.

    摘要翻译： 一种用于提高缓存性能的方法和系统。 高速缓存可以包括标签条目的阵列，其中每个标签条目包括用于指示其相关联的高速缓存行是否被重用，即被处理器请求或引用的附加位（“重用位”）。 通过跟踪高速缓存行是否被重用，在替换可被重用的数据（高速缓存行）之前，可以用新的传入高速缓存行替换可能不被重用的数据（高速缓存行）。 通过在替换可能被重用的数据之前替换高速缓冲存储器中可能不被重用的数据，可以提高高速缓存命中，从而提高性能。

    Memory system with apparatus and method to enable balanced bandwidth utilization
    30.
    发明授权
    Memory system with apparatus and method to enable balanced bandwidth utilization 失效
    具有使平衡带宽利用的装置和方法的存储器系统

    公开(公告)号：US07286543B2

    公开(公告)日：2007-10-23

    申请号：US10370550

    申请日：2003-02-20

    申请人： Brian M. Bass ,  Gordon T. Davis ,  Michael S. Siegel ,  Michael R. Trombley

    发明人： Brian M. Bass ,  Gordon T. Davis ,  Michael S. Siegel ,  Michael R. Trombley

    IPC分类号： H04L12/28 ,  H04J3/24

    CPC分类号： H04L49/9042 ,  H04L49/90 ,  H04L2012/5681

    摘要： A memory subsystem includes Data Store 0 and Data Store 1. Each data store is partitioned into N buffers, N>1. An increment of memory is formed by a buffer pair, with each buffer of the buffer pair being in a different data store. Two buffer pair formats are used in forming memory increments. A first format selects a first buffer from Data Store 0 and a second buffer from Data Store 1, while a second format selects a first buffer from Data Store 1 and a second buffer from Data Store 0. A controller selects a buffer pair for storing data based upon the configuration of data in a delivery mechanism, such as switch cell.

    摘要翻译： 存储器子系统包括数据存储0和数据存储1.每个数据存储分区为N个缓冲区，N> 1。 存储器的增量由缓冲器对形成，缓冲器对的每个缓冲器在不同的数据存储器中。 两个缓冲器对格式用于形成存储器增量。 第一格式从Data Store 0中选择第一个缓冲区，从Data Store 1中选择第二个缓冲区，而第二个格式从Data Store 1中选择第一个缓冲区，并从Data Store 0中选择一个第二个缓冲区。控制器选择一个用于存储数据的缓冲区 基于诸如交换单元之类的递送机制中的数据的配置。