Clock-edge modulated serial link with DC-balance control
    21.
    发明授权
    Clock-edge modulated serial link with DC-balance control 有权
    具有直流平衡控制的时钟调制串行链路

    公开(公告)号:US07627044B2

    公开(公告)日:2009-12-01

    申请号:US11264303

    申请日:2005-10-31

    IPC分类号: H04B3/00

    摘要: A battery powered computing device has a channel configured as a single direct current balanced differential channel. A signal transmitter is connected to the channel. The signal transmitter is configured to apply clock edge modulated signals to the channel, where the clock edge modulated signals include direct current balancing control signals. A signal receiver is connected to the channel. The signal receiver is configured to recover the direct current balancing control signals.

    摘要翻译: 电池供电的计算设备具有被配置为单个直流平衡差分通道的通道。 信号发射器连接到通道。 信号发射器被配置为将时钟边缘调制信号施加到信道,其中时钟边缘调制信号包括直流平衡控制信号。 信号接收器连接到通道。 信号接收器被配置为恢复直流平衡控制信号。

    Method and apparatus for sending auxiliary data on a TMDS-like link
    22.
    发明授权
    Method and apparatus for sending auxiliary data on a TMDS-like link 有权
    在类似TMDS的链路上发送辅助数据的方法和装置

    公开(公告)号:US07558326B1

    公开(公告)日:2009-07-07

    申请号:US09954663

    申请日:2001-09-12

    IPC分类号: H04B14/06 H04N7/04

    摘要: A communication system including a transmitter, a receiver, and a TMDS-like link, in which video data and auxiliary data (typically including timing data associated with other auxiliary data) are transmitted from the transmitter to the receiver, or in which video data are transmitted over the link from the transmitter to the receiver, and auxiliary data (typically including timing data associated with other auxiliary data) are transmitted from the receiver to the transmitter. In typical embodiments the auxiliary data include one or more streams of audio data. Other aspects are transmitters and receivers for use in such a system, methods for sending auxiliary data and video data over a TMDS-like link, methods for transmitting and recovering clocks for auxiliary data transmitted over such a link, methods for synchronizing auxiliary data transmitted over such a link with video data transmitted over such a link, and methods for generating clocks having frequency closely matching the rate at which the auxiliary data are transmitted over such a link.

    摘要翻译: 包括发射机,接收机和类似TMDS的链路的通信系统,其中视频数据和辅助数据(通常包括与其他辅助数据相关联的定时数据)从发射机发送到接收机,或者哪个视频数据是 通过从发射机到接收机的链路传输,并且辅助数据(通常包括与其他辅助数据相关联的定时数据)从接收机发射到发射机。 在典型实施例中,辅助数据包括一个或多个音频数据流。 其他方面是用于这种系统的发射机和接收机,用于通过类似TMDS的链路发送辅助数据和视频数据的方法,用于发送和恢复通过这种链路传输的辅助数据的时钟的方法,用于同步传输的辅助数据的方法 与通过这种链路发送的视频数据的这种链接,以及用于产生具有与辅助数据通过这种链路发送的速率非常匹配的频率的时钟的方法。

    Combining a clock signal and a data signal
    23.
    发明授权
    Combining a clock signal and a data signal 有权
    组合时钟信号和数据信号

    公开(公告)号:US07158593B2

    公开(公告)日:2007-01-02

    申请号:US10099533

    申请日:2002-03-15

    IPC分类号: H04L7/00

    摘要: A method of transmitting data in a system including at least one data channel and a separate clock channel is disclosed. The method involves combining a clock signal to be transmitted on the clock channel with a data signal to generate a combined clock and data signal. In one embodiment, the data signal has been generated from data words using an encoding scheme that shifts an energy spectrum of the data signal away from an energy spectrum of the clock signal. In another embodiment, the clock signal has a plurality of pulses each having a front edge and a back edge, and the data signal is modulated onto the clock signal by moving at least one edge (i.e. front or back or both) of the plurality of pulses, thereby to create a combined clock and data signal.

    摘要翻译: 公开了一种在包括至少一个数据信道和单独的时钟信道的系统中发送数据的方法。 该方法包括将要在时钟信道上发送的时钟信号与数据信号组合以产生组合的时钟和数据信号。 在一个实施例中,数据信号已经使用使数据信号的能谱偏离时钟信号的能谱的编码方案从数据字生成。 在另一个实施例中,时钟信号具有多个脉冲,每个脉冲具有前沿和后沿,并且数据信号通过移动多个脉冲的至少一个边缘(即,前面或背面或两者)被调制到时钟信号上 脉冲,从而创建一个组合的时钟和数据信号。

    Logic gates including diode-connected metal-oxide-semiconductor field-effect transistors (MOSFETS) to control input threshold voltage levels and switching transients of output logic signals
    24.
    发明授权
    Logic gates including diode-connected metal-oxide-semiconductor field-effect transistors (MOSFETS) to control input threshold voltage levels and switching transients of output logic signals 有权
    包括二极管连接的金属氧化物半导体场效应晶体管(MOSFET)的逻辑门,用于控制输入阈值电压电平和输出逻辑信号的切换瞬变

    公开(公告)号:US07058121B1

    公开(公告)日:2006-06-06

    申请号:US09989647

    申请日:2001-11-20

    IPC分类号: H04B1/38

    CPC分类号: H04L5/1423

    摘要: Logic gates are provided that include a diode-connected metal-oxide-semiconductor field-effect transistor (MOSFET) to produce a gate threshold voltage that differs from a mid-supply voltage level, while providing symmetry in the switching transients of the output logic signals. In one embodiment, the logic gate is a NAND gate. Use of a diode-connected n-type MOSFET in a ground path produces a threshold voltage level higher than the mid-supply voltage level. Use of a diode-connected p-type MOSFET in a supply voltage path produces a threshold voltage level lower than the mid-supply voltage level. In another embodiment, the logic gate is a NOR gate. Use of a diode-connected n-type MOSFET in a ground path produces a threshold voltage level higher than the mid-supply voltage level. Use of a diode-connected p-type MOSFET in a supply voltage path produces a threshold voltage level lower than the mid-supply voltage level.

    摘要翻译: 提供逻辑门,其包括二极管连接的金属氧化物半导体场效应晶体管(MOSFET),以产生不同于中间电源电压电平的栅极阈值电压,同时在输出逻辑信号的开关瞬变中提供对称性 。 在一个实施例中,逻辑门是NAND门。 在接地路径中使用二极管连接的n型MOSFET产生高于中间电源电压电平的阈值电压电平。 在电源电压路径中使用二极管连接的p型MOSFET产生低于中间电源电压电平的阈值电压电平。 在另一个实施例中,逻辑门是NOR门。 在接地路径中使用二极管连接的n型MOSFET产生高于中间电源电压电平的阈值电压电平。 在电源电压路径中使用二极管连接的p型MOSFET产生低于中间电源电压电平的阈值电压电平。

    Differential amplifiers using asymmetric transfer characteristics to suppress input noise in output logic signals
    25.
    发明授权
    Differential amplifiers using asymmetric transfer characteristics to suppress input noise in output logic signals 有权
    使用非对称传输特性的差分放大器抑制输出逻辑信号中的输入噪声

    公开(公告)号:US06985005B1

    公开(公告)日:2006-01-10

    申请号:US09989487

    申请日:2001-11-20

    IPC分类号: H03K17/16

    摘要: An output amplifier is provided for use in a bidirectional communications interface, for example, connecting a transmitter and a receiver to a transmission line. The output amplifier includes a differential amplifier pair connected to output circuitry. The differential amplifier pair receives differential data signal pairs from each of a transmission line and a transmitter. The output circuitry receives signals from the differential amplifier pair and, in response, forms single-ended output logic signals. The output amplifier suppresses electronic input noise throughput using an asymmetric transfer characteristic that offsets output signal logic levels with respect to input noise signal levels. The asymmetric transfer characteristic is produced by skewing a transfer characteristic of the differential amplifier pair using an asymmetrical transistor configuration at an output side of the differential amplifier pair. The output logic signals represent data received on the transmission line, and are provided to the receiver.

    摘要翻译: 输出放大器被提供用于双向通信接口,例如将发射器和接收器连接到传输线。 输出放大器包括连接到输出电路的差分放大器对。 差分放大器对从传输线和发送器中的每一个接收差分数据信号对。 输出电路从差分放大器对接收信号,作为响应,形成单端输出逻辑信号。 输出放大器使用偏移相对于输入噪声信号电平的输出信号逻辑电平的非对称传输特性来抑制电子输入噪声吞吐量。 非对称传输特性是通过在差分放大器对的输出侧使用不对称晶体管配置来歪斜差分放大器对的传输特性而产生的。 输出逻辑信号表示在传输线上接收的数据,并提供给接收机。

    Transmitter and receiver using asymmetric transfer characteristics in differential amplifiers to suppress noise
    26.
    发明授权
    Transmitter and receiver using asymmetric transfer characteristics in differential amplifiers to suppress noise 有权
    发射机和接收机使用差分放大器中的非对称传输特性来抑制噪声

    公开(公告)号:US07847583B2

    公开(公告)日:2010-12-07

    申请号:US12275686

    申请日:2008-11-21

    IPC分类号: H03K17/16

    摘要: An output amplifier is provided for use in a bidirectional communications interface, for example, connecting a transmitter and a receiver to a transmission line. The output amplifier includes a differential amplifier pair connected to output circuitry. The differential amplifier pair receives differential data signal pairs from each of a transmission line and a transmitter. The output circuitry receives signals from the differential amplifier pair and, in response, forms single-ended output logic signals. The output amplifier suppresses electronic input noise throughput using an asymmetric transfer characteristic that offsets output signal logic levels with respect to input noise signal levels. The asymmetric transfer characteristic is produced by skewing a transfer characteristic of the differential amplifier pair using an asymmetrical transistor configuration at an output side of the differential amplifier pair. The output logic signals represent data received on the transmission line, and are provided to the receiver.

    摘要翻译: 输出放大器被提供用于双向通信接口,例如将发射器和接收器连接到传输线。 输出放大器包括连接到输出电路的差分放大器对。 差分放大器对从传输线和发送器中的每一个接收差分数据信号对。 输出电路从差分放大器对接收信号,作为响应,形成单端输出逻辑信号。 输出放大器使用偏移相对于输入噪声信号电平的输出信号逻辑电平的非对称传输特性来抑制电子输入噪声吞吐量。 非对称传输特性是通过在差分放大器对的输出侧使用不对称晶体管配置来歪斜差分放大器对的传输特性而产生的。 输出逻辑信号表示在传输线上接收的数据,并提供给接收机。

    BI-DIRECTIONAL BRIDGE CIRCUIT HAVING HIGH COMMON MODE REJECTION AND HIGH INPUT SENSITIVITY
    27.
    发明申请
    BI-DIRECTIONAL BRIDGE CIRCUIT HAVING HIGH COMMON MODE REJECTION AND HIGH INPUT SENSITIVITY 有权
    具有高共模抑制和高输入灵敏度的双向电路

    公开(公告)号:US20100142419A1

    公开(公告)日:2010-06-10

    申请号:US12573847

    申请日:2009-10-05

    IPC分类号: H04B3/30

    摘要: A bidirectional communications interface is provided that connects a transmitter and a receiver, or a transceiver, to a transmission line. Under an embodiment, the bidirectional interface generates positive and negative polarity data signals using two separate differential amplifiers that receive differential signal pairs from each side of a differential link to the transmission line and the transmitter. The bidirectional interface controls common mode rejection in each of the separate differential amplifiers using bias signals generated in response to an output common mode feedback voltage from each of the differential amplifiers. An output amplifier combines the positive and negative polarity data signals to form single-ended output logic signals. The output logic signals represent data received on the transmission line, and are provided to the receiver.

    摘要翻译: 提供了将发射器和接收器或收发器连接到传输线的双向通信接口。 在一个实施例中,双向接口使用两个单独的差分放大器产生正极性和负极性数据信号,差分放大器从差分链路的每一侧接收到传输线和发射器的差分信号对。 双向接口通过响应于来自每个差分放大器的输出共模反馈电压产生的偏置信号来控制每个单独的差分放大器中的共模抑制。 输出放大器组合正极性和负极性数据信号,形成单端输出逻辑信号。 输出逻辑信号表示在传输线上接收的数据,并提供给接收机。

    Transmitter And Receiver Using Asymmetric Transfer Characteristics in Differential Amplifiers To Suppress Noise
    28.
    发明申请
    Transmitter And Receiver Using Asymmetric Transfer Characteristics in Differential Amplifiers To Suppress Noise 有权
    发射机和接收机使用差分放大器中的非对称传输特性抑制噪声

    公开(公告)号:US20090137208A1

    公开(公告)日:2009-05-28

    申请号:US12275686

    申请日:2008-11-21

    摘要: An output amplifier is provided for use in a bidirectional communications interface, for example, connecting a transmitter and a receiver to a transmission line. The output amplifier includes a differential amplifier pair connected to output circuitry. The differential amplifier pair receives differential data signal pairs from each of a transmission line and a transmitter. The output circuitry receives signals from the differential amplifier pair and, in response, forms single-ended output logic signals. The output amplifier suppresses electronic input noise throughput using an asymmetric transfer characteristic that offsets output signal logic levels with respect to input noise signal levels. The asymmetric transfer characteristic is produced by skewing a transfer characteristic of the differential amplifier pair using an asymmetrical transistor configuration at an output side of the differential amplifier pair. The output logic signals represent data received on the transmission line, and are provided to the receiver.

    摘要翻译: 输出放大器被提供用于双向通信接口,例如将发射器和接收器连接到传输线。 输出放大器包括连接到输出电路的差分放大器对。 差分放大器对从传输线和发送器中的每一个接收差分数据信号对。 输出电路从差分放大器对接收信号,作为响应,形成单端输出逻辑信号。 输出放大器使用偏移相对于输入噪声信号电平的输出信号逻辑电平的非对称传输特性来抑制电子输入噪声吞吐量。 非对称传输特性是通过在差分放大器对的输出侧使用不对称晶体管配置来歪斜差分放大器对的传输特性而产生的。 输出逻辑信号表示在传输线上接收的数据,并提供给接收机。

    Bi-directional bridge circuit having high common mode rejection and high input sensitivity

    公开(公告)号:US20060256744A1

    公开(公告)日:2006-11-16

    申请号:US11441669

    申请日:2006-05-25

    IPC分类号: H04B1/58 H04B3/30

    摘要: A bidirectional communications interface is provided that connects a transmitter and a receiver, or a transceiver, to a transmission line. Under an embodiment, the bidirectional interface generates positive and negative polarity data signals using two separate differential amplifiers that receive differential signal pairs from each side of a differential link to the transmission line and the transmitter. The bidirectional interface controls common mode rejection in each of the separate differential amplifiers using bias signals generated in response to an output common mode feedback voltage from each of the differential amplifiers. An output amplifier combines the positive and negative polarity data signals to form single-ended output logic signals. The output logic signals represent data received on the transmission line, and are provided to the receiver.

    Bi-directional bridge circuit having high common mode rejection and high input sensitivity
    30.
    发明授权
    Bi-directional bridge circuit having high common mode rejection and high input sensitivity 有权
    具有高共模抑制和高输入灵敏度的双向电桥电路

    公开(公告)号:US08116240B2

    公开(公告)日:2012-02-14

    申请号:US12573847

    申请日:2009-10-05

    IPC分类号: H04B3/20 H04B1/52 H04B1/58

    摘要: A bidirectional communications interface is provided that connects a transmitter and a receiver, or a transceiver, to a transmission line. Under an embodiment, the bidirectional interface generates positive and negative polarity data signals using two separate differential amplifiers that receive differential signal pairs from each side of a differential link to the transmission line and the transmitter. The bidirectional interface controls common mode rejection in each of the separate differential amplifiers using bias signals generated in response to an output common mode feedback voltage from each of the differential amplifiers. An output amplifier combines the positive and negative polarity data signals to form single-ended output logic signals. The output logic signals represent data received on the transmission line, and are provided to the receiver.

    摘要翻译: 提供了将发射器和接收器或收发器连接到传输线的双向通信接口。 在一个实施例中,双向接口使用两个单独的差分放大器产生正极性和负极性数据信号,差分放大器从差分链路的每一侧接收到传输线和发射器的差分信号对。 双向接口通过响应于来自每个差分放大器的输出共模反馈电压产生的偏置信号来控制每个单独的差分放大器中的共模抑制。 输出放大器组合正极性和负极性数据信号,形成单端输出逻辑信号。 输出逻辑信号表示在传输线上接收的数据,并提供给接收机。