公开(公告)号：US11232352B2

公开(公告)日：2022-01-25

申请号：US16037060

申请日：2018-07-17

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Brent Buchanan ,  John Paul Strachan ,  Le Zheng

IPC: G06N3/04 ,  G06N3/063 ,  G06N3/08

Abstract: A circuit for a neuron of a multi-stage compute process is disclosed. The circuit comprises a weighted charge packet (WCP) generator. The circuit may also include a voltage divider controlled by a programmable resistance component (e.g., a memristor). The WCP generator may also include a current mirror controlled via the voltage divider and arrival of an input spike signal to the neuron. WCPs may be created to represent the multiply function of a multiply accumulate processor. The WCPs may be supplied to a capacitor to accumulate and represent the accumulate function. The value of the WCP may be controlled by the length of the spike in signal times the current supplied through the current mirror. Spikes may be asynchronous. Memristive components may be electrically isolated from input spike signals so their programmed conductance is not affected. Positive and negative spikes and WCPs for accumulation may be supported.

公开(公告)号：US20210193222A1

公开(公告)日：2021-06-24

申请号：US16065364

申请日：2016-01-26

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Emmanuelle J. Merced Grafals ,  Brent Buchanan ,  Le Zheng

IPC: G11C13/00

Abstract: In one example in accordance with the present disclosure a memristive bit cell is described. The memristive bit cell includes a memristive device switchable between states. The memristive device is to store information. The memristive bit cell also includes a first switch regulating component coupled to the memristive device. The first switch regulating component enforces compliance of the memristive device with a first property threshold when switching between states in a first direction. The first property threshold corresponds to a state of the memristive device. The memristive bit cell also includes a second switch regulating component coupled to the memristive device. The second switch regulating component enforces compliance of the memristive device with a second property threshold when switching between states in a second direction. The second property threshold corresponds to a state of the memristive device.

公开(公告)号：US10418103B1

公开(公告)日：2019-09-17

申请号：US15958903

申请日：2018-04-20

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Brent Buchanan ,  John Paul Strachan ,  Le Zheng ,  Catherine Graves

IPC: G11C15/00 ,  G11C15/04 ,  G11C13/00 ,  G11C7/06

Abstract: According to examples, an apparatus may include a ternary content addressable memory (TCAM) including a plurality of TCAM bit cells connected in a row along a match line. Each of the TCAM bit cells may store a bit of a TCAM word and the TCAM bit cells may drive a digital signal over the match line in response to a search word matching the TCAM word. The apparatus may include a resistive random-access memory (RRAM) comprising a row of RRAM bit cells connected to the TCAM via the match line. Each of the RRAM bit cells may store a bit of a RRAM word. The RRAM bit cells may output the RRAM word in response to the TCAM bit cells driving the digital signal over the match line.

公开(公告)号：US10332592B2

公开(公告)日：2019-06-25

申请号：US15570951

申请日：2016-03-11

Applicant: Hewlett Packard Enterprise Development LP

Inventor： John Paul Strachan ,  Brent Buchanan ,  Le Zheng

IPC: G11C11/54 ,  G06F9/06 ,  G06N3/063 ,  G11C13/00 ,  G11C7/10 ,  G06N3/04

Abstract: Examples herein relate to hardware accelerators for calculating node values of neural networks. An example hardware accelerator may include a crossbar array programmed to calculate node values of a neural network and a current comparator to compare an output current from the crossbar array to a threshold current according to an update rule to generate new node values. The crossbar array has a plurality of row lines, a plurality of column lines, and a memory cell coupled between each unique combination of one row line and one column line, where the memory cells are programmed according to a weight matrix. The plurality of row lines are to receive an input vector of node values, and the plurality of column lines are to deliver an output current to be compared with the threshold current.

公开(公告)号：US10037804B1

公开(公告)日：2018-07-31

申请号：US15418040

申请日：2017-01-27

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Brent Buchanan ,  Le Zheng ,  John Paul Strachan

IPC: G11C11/00 ,  G11C13/00 ,  G06F17/16

Abstract: Examples disclosed herein relate to programming a first conductance of a first resistive memory device based on a first target value. The first conductance of the first resistive memory device is measured to determine a deviation of the first resistive memory device from the first target value. A second target value of a second resistive memory device is adjusted based on the deviation, and a second conductance of the second resistive memory device is programmed based on the adjusted second target value.

公开(公告)号：US10007517B2

公开(公告)日：2018-06-26

申请号：US15281280

申请日：2016-09-30

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Brent Buchanan ,  Le Zheng

IPC: G06F9/30 ,  G06N3/04 ,  G06N3/063

CPC classification number: G06F9/3001 ,  G06F9/30 ,  G06N3/0635

Abstract: An example device may include multiply-accumulate circuitry and voltage-tracking modulator circuitry. The multiply-accumulate circuitry may be to increase and decrease an accumulation voltage held by an accumulator based on a number of input signals. The voltage-tracking modulator circuitry may be to generate an output signal based on the accumulation voltage, wherein the output signal is a continuous-time binary signal that tracks changes of the accumulation voltage by varying pulse widths of the output signal. The example device may be used as a neuron in a neural network.

公开(公告)号：US09847132B1

公开(公告)日：2017-12-19

申请号：US15222234

申请日：2016-07-28

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Le Zheng ,  Brent Buchanan ,  John Paul Strachan

IPC: G11C15/00 ,  G11C15/04

CPC classification number: G11C15/046 ,  G11C13/0069 ,  G11C2213/74 ,  G11C2213/79

Abstract: An example ternary content addressable memory. A bit cell of the memory may include first and second memristors, with a first terminal of the first memristor being connected to a first terminal of the second memristor via a node, a second terminal of the first memristor being switchably connected to a first data line, and a second terminal of the second memristor being switchably connected to a second data line. The bit cell may also include a match-line transistor that is connected between a first rail and a match line, with a gate of the match-line transistor being connected to the node.

公开(公告)号：US09691479B1

公开(公告)日：2017-06-27

申请号：US15142995

申请日：2016-04-29

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Emmanuelle J. Merced Grafals ,  Brent Buchanan ,  Le Zheng

IPC: G11C11/00 ,  G11C13/00

CPC classification number: G11C13/0069 ,  G11C13/0002 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/003 ,  G11C13/004 ,  G11C2013/0076 ,  G11C2013/0088 ,  G11C2013/0092 ,  G11C2213/71 ,  G11C2213/74 ,  G11C2213/79

Abstract: A method of operating a plurality of memristive cells coupled as a memristor array includes initializing a first select line, and, in parallel for a number of memristor cells in the first select line, determining whether a level of conductance of the memristor cells in the first select line are within a tolerance of a reference conductance, and, in response to a determination that the level of conductance is not within the tolerance of the reference conductance, adjusting the level of conductance for the memristor cells in the first select line.

公开(公告)号：US10706922B2

公开(公告)日：2020-07-07

申请号：US16063804

申请日：2016-01-26

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Brent Buchanan ,  Le Zheng ,  John Paul Strachan

IPC: G11C13/00 ,  G06G7/16 ,  G11C11/16 ,  G06F17/16

Abstract: In one example in accordance with the present disclosure a device is described. The device includes a cross-bar array of memristive elements. Each memristive element has a conductance value. The device also includes a column of offset elements. An offset element is coupled to a row of memristive elements and has a conductance value. The device also includes a number of accumulation elements. An accumulation element is coupled to a column of memristive elements. The accumulation element collects an intermediate output from the column and subtracts from the intermediate output an output from the column of offset elements.

公开(公告)号：US20200026995A1

公开(公告)日：2020-01-23

申请号：US16037060

申请日：2018-07-17

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Brent Buchanan ,  John Paul Strachan ,  Le Zheng

IPC: G06N3/08 ,  G06N3/063 ,  G06N3/04

Abstract: A circuit for a neuron of a multi-stage compute process is disclosed. The circuit comprises a weighted charge packet (WCP) generator. The circuit may also include a voltage divider controlled by a programmable resistance component (e.g., a memristor). The WCP generator may also include a current mirror controlled via the voltage divider and arrival of an input spike signal to the neuron. WCPs may be created to represent the multiply function of a multiply accumulate processor. The WCPs may be supplied to a capacitor to accumulate and represent the accumulate function. The value of the WCP may be controlled by the length of the spike in signal times the current supplied through the current mirror. Spikes may be asynchronous. Memristive components may be electrically isolated from input spike signals so their programmed conductance is not affected. Positive and negative spikes and WCPs for accumulation may be supported.