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公开(公告)号：US10770140B2
公开(公告)日：2020-09-08
申请号：US16065771
申请日：2016-01-27
Applicant: Hewlett Packard Enterprise Development LP
Inventor： John Paul Strachan , Brent Buchanan , Le Zheng
Abstract: The present disclosure provides a memristive array. The array includes a number of memristive devices. A memristive device is switchable between states and is to store information. The memristive array also includes a parallel reset control device coupled to the number of memristive devices in parallel. The parallel reset control device regulates a resetting operation for the number of memristive devices by regulating current flow through target memristive devices.
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公开(公告)号：US20200167530A1
公开(公告)日：2020-05-28
申请号：US16072279
申请日：2016-02-25
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Brent Buchanan , Le Zheng
Abstract: In one example in accordance with the present disclosure a device is described. The device includes at least two memristive cells. Each memristive cell includes a memristive element to store one component of a complex weight value. The device also includes a real input multiplier coupled to the memristive element to multiply an output signal of the memristive element with a real component of an input signal. An imaginary input multiplier of the device is coupled to the memristive element to multiply the output signal of the memristive element with an imaginary component of the input signal.
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公开(公告)号：US10261487B1
公开(公告)日：2019-04-16
申请号：US15885193
申请日：2018-01-31
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Brent Buchanan , John Paul Strachan , Le Zheng
IPC: G05B19/045 , G11C15/04
Abstract: An example finite state machine may include a content-addressable memory. The content-addressable memory may include blocks that respectively store input-terms of the finite state machine. The finite state machine may be configured to, for each received input: select a subset of the blocks of the content addressable memory to enable for searching, the subset being selected based on a current state of the finite state machine, and determine a next state of the finite state machine by searching the currently enabled subset of blocks of the content addressable memory based on the input.
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公开(公告)号：US10180820B2
公开(公告)日：2019-01-15
申请号：US15282021
申请日：2016-09-30
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Brent Buchanan , Le Zheng , John Paul Strachan
Abstract: In some examples, a method may be performed by a multiply-accumulate circuit. As part of the method a row driver of the multiply-accumulate circuit may drive a row value line based on an input vector bit of an input vector received by the row driver. The row driver may also drive a row line that controls a corresponding memristor according to the input vector bit. The corresponding memristor may store a weight value bit of a weight value to apply to the input vector for a multiply-accumulate operation. The method may further include a sense amplifier generating an output voltage based on a current output from the corresponding memristor and counter circuitry adjusting a counter value that represents a running total of the multiply-accumulate operation based on the row value line, the output voltage generated by the sense amplifier, or a combination of both.
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公开(公告)号：US09953728B2
公开(公告)日：2018-04-24
申请号：US15216589
申请日：2016-07-21
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Emmanuelle J Merced Grafals , Brent Buchanan , Le Zheng
CPC classification number: G11C29/789 , G11C13/0021 , H01L45/04 , H01L45/16
Abstract: Examples include a resistive random access memory (RRAM) array to support a redundant column. Some examples include an RRAM cell at a cross point of a column line and a row line of the RRAM array. A first column line may be coupled to a first input of a first current-steering multiplexer and the first current-steering multiplexer may have an output coupled to a first current sense amplifier and a select input coupled to a first column select signal. A second column line may be coupled to a second input of the first current-steering multiplexer and coupled to a first input of a second current-steering multiplexer. The second current-steering multiplexer may have an output coupled to a second current sense amplifier and a select input coupled to a second column select signal. A third column line may be coupled to a second input of the second current-steering multiplexer.
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Patent Agency Ranking
公开(公告)号：US20180040374A1
公开(公告)日：2018-02-08
申请号：US15228559
申请日：2016-08-04
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Le Zheng , Brent Buchanan , John Paul Strachan
IPC: G11C15/04
CPC classification number: G11C15/046
Abstract: An example ternary content addressable memory. A bit cell of the memory may include a first memristor that has a first terminal that is connected to a first data line and a second terminal that is selectively connected to a second data line via a first switching transistor. The bit cell may also include a second memristor that has a first terminal that is connected to a third data line and a second terminal that is selectively connected to a fourth data line via a second switching transistor. The bit cell may also include a first match-line transistor and a second match-line transistor that are connected in series between a first rail and a match line, with a gate of the first match-line transistor being connected to the second terminal of the first memristor, and a gate of the second match-line transistor being connected to the second terminal of the second memristor.
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公开(公告)号：US09721661B1
公开(公告)日：2017-08-01
申请号：US15216011
申请日：2016-07-21
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Brent Buchanan , Le Zheng , John Paul Strachan
IPC: G11C15/04
CPC classification number: G11C15/046 , G11C13/0002 , G11C13/0007 , G11C15/04
Abstract: An example content addressable memory. A bit cell of the memory may include a memristor and a switching transistor that are connected in series between a first data line and a second data line. The bit cell may also include a match-line transistor connected between a match line and a rail. A gate of the match-line transistor may be connected to a common node of the memristor and the switching transistor. The switching transistor may be sized such that its channel resistance when on is between a resistance associated with a low-resistance state of the memristor and a resistance associated with a high-resistance state of the memristor.
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公开(公告)号：US10216720B2
公开(公告)日：2019-02-26
申请号：US15336907
申请日：2016-10-28
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Brent Buchanan , Le Zheng , John Paul Strachan
IPC: G06F17/27
Abstract: Comparators may be associated with dictionary entries. In one aspect, a dictionary entry may store a dictionary word. A register may store an input word. A comparator associated with the dictionary entry may compare the dictionary word and the input word. The comparison may be a bit by bit comparison. The comparator may output a signal indicating if the dictionary word is less than the input word, equal to the input word, or greater than the input word. The output may indicate indeterminate when the comparison is not yet complete.
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公开(公告)号：US10089574B2
公开(公告)日：2018-10-02
申请号：US15264768
申请日：2016-09-14
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Brent Buchanan , Sity Lam , Le Zheng
Abstract: Examples disclosed herein relate to neuron circuits and methods for generating neuron circuit outputs. In some of the disclosed examples, a neuron circuit includes a memristor and first and second current mirrors. The first current mirror may source a first current through the memristor and the second current mirror may sink a second current through the memristor. The memristor may generate a voltage output as a function of the sourced first current and the sunk second current through the memristor.
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公开(公告)号：US20180114569A1
公开(公告)日：2018-04-26
申请号：US15570951
申请日：2016-03-11
Applicant: Hewlett Packard Enterprise Development LP
Inventor： John Paul Strachan , Brent Buchanan , Le Zheng
CPC classification number: G11C11/54 , G06F9/06 , G06N3/0454 , G06N3/0635 , G11C7/1006 , G11C7/1012 , G11C13/0007 , G11C13/0069
Abstract: Examples herein relate to hardware accelerators for calculating node values of neural networks. An example hardware accelerator may include a crossbar array programmed to calculate node values of a neural network and a current comparator to compare an output current from the crossbar array to a threshold current according to an update rule to generate new node values. The crossbar array has a plurality of row lines, a plurality of column lines, and a memory cell coupled between each unique combination of one row line and one column line, where the memory cells are programmed according to a weight matrix. The plurality of row lines are to receive an input vector of node values, and the plurality of column lines are to deliver an output current to be compared with the threshold current.
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