Abstract:
An input/output apparatus of a multiplexer is provided, including: a main tap and at least two branch taps of the main tap, where each of the at least two branch taps is configured to couple to a different resonant cavity in the multiplexer, and the at least two branch taps include a first branch tap and a second branch tap; a coupling polarity of the first branch tap is opposite to that of the second branch tap; and a coupling calculation frequency of the second branch tap is closest to a coupling calculation frequency of the first branch tap. The input/output apparatus of the multiplexer enables two channels with closest frequencies to use different coupling polarities. Because the coupling polarities are different, signals naturally do not interfere with each other, and signal interference between channels is eliminated in principle. The embodiments of the present disclosure further provide a corresponding multiplexer.
Abstract:
A method and an apparatus for managing one or more physical network interface cards and a physical host are provided. One or more virtual network interface cards are created, where each of the virtual network interface cards has a standard network interface card feature and an operation interface; the one or more virtual network interface cards are separately associated with one or more function modules of the physical network interface cards; and the physical network interface cards are managed by managing the one or more virtual network interface cards. In this way, differences in underlying hardware are shielded for an upper layer, and convenient and efficient centralized management are provided, thereby further improving network resource utilization.
Abstract:
A data cache method, device, and system in a multi-node system are provided. The method includes: dividing a cache area of a cache medium into multiple sub-areas, where each sub-area is corresponding to a node in the system; dividing each of the sub-areas into a thread cache area and a global cache area; when a process reads a file, detecting a read frequency of the file; when the read frequency of the file is greater than a first threshold and the size of the file does not exceed a second threshold, caching the file in the thread cache area; or when the read frequency of the file is greater than the first threshold and the size of the file exceeds the second threshold, caching the file in the global cache area. Thus overheads of remote access of a system are reduced, and I/O performance of the system is improved.
Abstract:
The present invention provides a network interface adapter registration method, driver, and server, where the method includes: registering, by a driver of a server, a network interface adapter with a kernel of the server as a physical network device; and registering, by the driver, apart of or all hardware queue receiving and sending groups of the network interface adapter with the kernel of the server as virtual network devices, where the physical network device is configured to manage the network interface adapter and all the virtual network devices, and each of the virtual network devices is configured to receive or send data of an application or a chip in the server. The foregoing method resolves a problem in the prior art that management and a direct operation cannot be performed on a single hardware queue of the network interface adapter.
Abstract:
A method for managing a processor includes: obtaining an online request of a processor of a computer system; collecting lock contention information of the computer system if a lock contention status flag indicates a non-lock thrashing status; determining whether the computer system is in a lock thrashing status according to the lock contention information; and accepting the online request if it is determined that the computer system is in a non-lock thrashing status. By using the management method according to embodiments of the present application, processor performance degradation and a waste of idle processor resources that are caused by the case that the computer system is in a lock thrashing status are prevented, thereby improving utilization efficiency of processor resources and promoting overall performance of the computer system.
Abstract:
A method includes: A basic application layer sends first information that includes a first business requirement and a first port to a basic service layer. The basic service layer sends second information that includes the first business requirement, a first broadcast business channel, and a logical channel type to an access layer. The first broadcast business channel is determined based on the first information. The access layer supports a first access technology that is determined, based on the first business requirement, from a plurality of access technologies supported by the access layer. The access layer sends a first mapping relationship that indicates the first broadcast business channel and a first logical channel to the basic service layer. The first logical channel is a logical channel that supports the first access technology and that is determined based on the second information.
Abstract:
A terminal device registration method and a device, where the method includes sending upstream registration window information to a terminal device, where the upstream registration window information indicates a starting position of an upstream registration window to the terminal device, receiving an upstream access signal sent by the terminal device from the starting position of the upstream registration window, where the upstream access signal includes a correlation sequence symbol and at least one orthogonal frequency division multiplexing (OFDM) symbol following the correlation sequence symbol, the correlation sequence symbol is constituted by a first sequence that meets a preset condition, and the at least one OFDM symbol modulates access information by means of differential phase modulation in a frequency domain, and performing upstream ranging according to the starting position of the upstream registration window and the correlation sequence symbol.
Abstract:
An apparatus for despreading in an optical domain configured to split a received optical signal into a first optical signal and a second optical signal, perform phase deflection on the second optical signal, output a third optical signal, perform phase deflection on the first optical signal and the third optical signal, output a fourth optical signal and a fifth optical signal to a balanced receiver, and superimpose the fourth optical signal and the fifth optical signal to generate a first electrical signal. A multiplication operation in conventional code division multiple access (CDMA) despreading is transferred from an electrical domain to an optical domain such that a chip rate can be easily raised to 20 gigahertz (GHz) or even to 25 GHz, a maximum rate of 100 gigabits per second (Gbps) can be provided in a single wavelength, and a user requirement for high bandwidth can be met.
Abstract:
A time synchronization method includes obtaining a first BLUETOOTH packet from a master device, where the first BLUETOOTH packet carries first time stamp information, and the first time stamp information indicates a sending moment t1 that is of the first BLUETOOTH packet and that is determined based on a clock of the master device; and correcting a local time of a slave device based on the first time stamp information.
Abstract:
An apparatus for despreading in an optical domain configured to split a received optical signal into a first optical signal and a second optical signal, perform phase deflection on the second optical signal, output a third optical signal, perform phase deflection on the first optical signal and the third optical signal, output a fourth optical signal and a fifth optical signal to a balanced receiver, and superimpose the fourth optical signal and the fifth optical signal to generate a first electrical signal. A multiplication operation in conventional code division multiple access (CDMA) despreading is transferred from an electrical domain to an optical domain such that a chip rate can be easily raised to 20 gigahertz (GHz) or even to 25 GHz, a maximum rate of 100 gigabits per second (Gbps) can be provided in a single wavelength, and a user requirement for high bandwidth can be met.