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    Semiconductor device and method of fabricating the same
    21.
    发明授权
    Semiconductor device and method of fabricating the same 有权
    半导体装置及其制造方法

    公开(公告)号：US07638433B2

    公开(公告)日：2009-12-29

    申请号：US11965420

    申请日：2007-12-27

    申请人： Jong-Ho Yun ,  Gil-Heyun Choi ,  Byung-Hee Kim ,  Hyun-Su Kim ,  Eun-Ok Lee

    发明人： Jong-Ho Yun ,  Gil-Heyun Choi ,  Byung-Hee Kim ,  Hyun-Su Kim ,  Eun-Ok Lee

    IPC分类号： H01L21/302 ,  H01L21/461 ,  H01L29/40

    CPC分类号： H01L21/28097 ,  H01L29/4975 ,  H01L29/66545

    摘要： A method of fabricating a semiconductor device includes forming a preliminary gate pattern on a semiconductor substrate. The preliminary gate pattern includes a gate oxide pattern, a conductive pattern, and a sacrificial insulating pattern. The method further includes forming spacers on opposite sidewalls of the preliminary gate pattern, forming an interlayer dielectric pattern to expose the sacrificial insulating pattern, removing the sacrificial insulating pattern to form an opening to expose the conductive pattern, transforming the conductive pattern into a metal silicide layer and forming a metal barrier pattern along an inner profile of the opening and a metal conductive pattern to fill the opening including the metal barrier pattern. The metal silicide layer and the metal conductive pattern constitute a gate electrode.

    摘要翻译： 制造半导体器件的方法包括在半导体衬底上形成初步栅极图案。 初步栅极图案包括栅极氧化物图案，导电图案和牺牲绝缘图案。 该方法还包括在初步栅极图案的相对侧壁上形成间隔物，形成层间电介质图案以暴露牺牲绝缘图案，去除牺牲绝缘图案以形成露出导电图案的开口，将导电图案转变为金属硅化物 并且沿着开口的内部轮廓形成金属阻挡图案和金属导电图案以填充包括金属阻挡图案的开口。 金属硅化物层和金属导电图案构成栅电极。

    Semiconductor device including upper and lower transistors and interconnection between upper and lower transistors
    24.
    发明授权
    Semiconductor device including upper and lower transistors and interconnection between upper and lower transistors 有权
    包括上和下晶体管的半导体器件和上和下晶体管之间的互连

    公开(公告)号：US07381989B2

    公开(公告)日：2008-06-03

    申请号：US11368418

    申请日：2006-03-07

    申请人： Hyun-Su Kim ,  Gil-Heyun Choi ,  Jong-Ho Yun ,  Sug-Woo Jung ,  Eun-Ji Jung

    发明人： Hyun-Su Kim ,  Gil-Heyun Choi ,  Jong-Ho Yun ,  Sug-Woo Jung ,  Eun-Ji Jung

    IPC分类号： H01L29/76 ,  H01L31/036 ,  H01L31/112

    CPC分类号： H01L27/0688 ,  H01L21/8221

    摘要： A stacked semiconductor device comprises a lower transistor formed on a semiconductor substrate, a lower interlevel insulation film formed on the semiconductor substrate over the lower transistor, an upper transistor formed on the lower interlayer insulation film over the lower transistor, and an upper interlevel insulation film formed on the lower interlevel insulation film over the upper transistor. The stacked semiconductor device further comprises a contact plug connected between a drain or source region of the lower transistor and a source or drain region of the upper transistor, and an extension layer connected to a lateral face of the source or drain region of the upper transistor to enlarge an area of contact between the source or drain region of the upper transistor and a side of the contact plug.

    摘要翻译： 叠层半导体器件包括形成在半导体衬底上的下晶体管，形成在半导体衬底上的下层晶体管上的下层间绝缘膜，形成在下晶体管上的下层间绝缘膜上的上晶体管，以及上层间绝缘膜 形成在上层晶体管上的较低层间绝缘膜上。 叠层半导体器件还包括连接在下晶体管的漏极或源极区域与上部晶体管的源极或漏极区域之间的接触插塞以及连接到上部晶体管的源极或漏极区域的侧面的延伸层 以扩大上部晶体管的源极或漏极区域与接触插塞的一侧之间的接触面积。

    Methods of forming semiconductor devices having stacked transistors and related devices
    25.
    发明申请
    Methods of forming semiconductor devices having stacked transistors and related devices 失效
    形成具有堆叠晶体管和相关器件的半导体器件的方法

    公开(公告)号：US20060246709A1

    公开(公告)日：2006-11-02

    申请号：US11398192

    申请日：2006-04-05

    申请人： Hyun-Su Kim ,  Gil-Heyun Choi ,  Jong-Ho Yun ,  Sug-Woo Jung ,  Eun-Ji Jung

    发明人： Hyun-Su Kim ,  Gil-Heyun Choi ,  Jong-Ho Yun ,  Sug-Woo Jung ,  Eun-Ji Jung

    IPC分类号： H01L21/4763 ,  H01L29/00

    CPC分类号： H01L21/8221 ,  H01L21/28518 ,  H01L21/76829 ,  H01L21/76898 ,  H01L27/0688 ,  Y10S257/903

    摘要： A method of forming a semiconductor device may include forming an interlayer insulating layer on a semiconductor substrate, and the interlayer insulating layer may have a contact hole therein exposing a portion of the semiconductor substrate. A single crystal semiconductor plug may be formed in the contact hole and on portions of the interlayer insulating layer adjacent the contact hole opposite the semiconductor substrate, and portions of the interlayer insulating layer opposite the semiconductor substrate may be free of the single crystal semiconductor plug. Portions of the single crystal semiconductor plug in the contact hole may be removed while maintaining portions of the single crystal semiconductor plug on portions of the interlayer insulating layer adjacent the contact hole as a single crystal semiconductor contact pattern. After removing portions of the single crystal semiconductor plug, a single crystal semiconductor layer may be formed on the interlayer insulating layer and on the single crystal semiconductor contact pattern. A second interlayer insulating layer may be formed on the single crystal semiconductor layer, and a common contact hole may be formed through the second interlayer insulating layer, through the single crystal semiconductor layer, and through the first interlayer insulating layer to expose a portion of semiconductor substrate. In addition, a conductive contact plug may be formed in the common contact hole in contact with the semiconductor substrate. Related devices are also discussed.

    摘要翻译： 形成半导体器件的方法可以包括在半导体衬底上形成层间绝缘层，并且层间绝缘层可以具有暴露半导体衬底的一部分的接触孔。 可以在接触孔中和在与半导体衬底相对的接触孔附近的层间绝缘层的部分上形成单晶半导体插塞，并且与半导体衬底相对的部分层间绝缘层可以不含单晶半导体插头。 可以去除接触孔中的单晶半导体插塞的部分，同时将单晶半导体插塞的部分保持在与接触孔相邻的层间绝缘层的部分上作为单晶半导体接触图案。 在去除单晶半导体插头的部分之后，可以在层间绝缘层和单晶半导体接触图案上形成单晶半导体层。 可以在单晶半导体层上形成第二层间绝缘层，并且可以通过单晶半导体层通过第二层间绝缘层形成公共接触孔，并且通过第一层间绝缘层暴露半导体的一部分 基质。 此外，可以在与半导体衬底接触的公共接触孔中形成导电接触插塞。 还讨论了相关设备。

    METHOD OF FORMING SEMICONDUCTOR DEVICE HAVING STACKED TRANSISTORS
    26.
    发明申请
    METHOD OF FORMING SEMICONDUCTOR DEVICE HAVING STACKED TRANSISTORS 有权
    形成具有堆叠晶体管的半导体器件的方法

    公开(公告)号：US20090280605A1

    公开(公告)日：2009-11-12

    申请号：US12503556

    申请日：2009-07-15

    申请人： Hyun-Su Kim ,  Gil-Heyun Choi ,  Jong-Ho Yun ,  Sug-Woo Jung ,  Eun-Ji Jung

    发明人： Hyun-Su Kim ,  Gil-Heyun Choi ,  Jong-Ho Yun ,  Sug-Woo Jung ,  Eun-Ji Jung

    IPC分类号： H01L21/84 ,  H01L21/44

    CPC分类号： H01L21/28518 ,  H01L21/76898 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/11 ,  H01L27/1108

    摘要： There is provided a method of forming a semiconductor device having stacked transistors. When farming a contact hole for connecting the stacked transistors to each other, ohmic layers on the bottom and the sidewall of the common contact hole are separately formed. As a result, the respective ohmic layers are optimally formed to meet requirements or conditions. Accordingly, the contact resistance of the common contact may be minimized so that it is possible to enhance the speed of the semiconductor device.

    摘要翻译： 提供了一种形成具有堆叠晶体管的半导体器件的方法。 当种植用于将堆叠的晶体管彼此连接的接触孔时，共同接触孔的底部和侧壁上的欧姆层是分开形成的。 结果，各个欧姆层被最佳地形成以满足要求或条件。 因此，公共接点的接触电阻可以最小化，从而可以提高半导体器件的速度。

    Semiconductor Devices Having Stacked Structures
    28.
    发明申请
    Semiconductor Devices Having Stacked Structures 失效
    具有堆叠结构的半导体器件

    公开(公告)号：US20080315312A1

    公开(公告)日：2008-12-25

    申请号：US12204420

    申请日：2008-09-04

    申请人： Hyun-Su Kim ,  Gil-Heyun Choi ,  Jong-Ho Yun ,  Sug-Woo Jung ,  Eun-Ji Jung

    发明人： Hyun-Su Kim ,  Gil-Heyun Choi ,  Jong-Ho Yun ,  Sug-Woo Jung ,  Eun-Ji Jung

    IPC分类号： H01L27/12

    CPC分类号： H01L21/8221 ,  H01L21/28518 ,  H01L21/76829 ,  H01L21/76898 ,  H01L27/0688 ,  Y10S257/903

    摘要： A method of forming a semiconductor device may include forming an interlayer insulating layer on a semiconductor substrate, and the interlayer insulating layer may have a contact hole therein exposing a portion of the semiconductor substrate. A single crystal semiconductor plug may be formed in the contact hole and on portions of the interlayer insulating layer adjacent the contact hole opposite the semiconductor substrate, and portions of the interlayer insulating layer opposite the semiconductor substrate may be free of the single crystal semiconductor plug. Portions of the single crystal semiconductor plug in the contact hole may be removed while maintaining portions of the single crystal semiconductor plug on portions of the interlayer insulating layer adjacent the contact hole as a single crystal semiconductor contact pattern. After removing portions of the single crystal semiconductor plug, a single crystal semiconductor layer may be formed on the interlayer insulating layer and on the single crystal semiconductor contact pattern. A second interlayer insulating layer may be formed on the single crystal semiconductor layer, and a common contact hole may be formed through the second interlayer insulating layer, through the single crystal semiconductor layer, and through the first interlayer insulating layer to expose a portion of semiconductor substrate. In addition, a conductive contact plug may be formed in the common contact hole in contact with the semiconductor substrate. Related devices are also discussed.

    摘要翻译： 形成半导体器件的方法可以包括在半导体衬底上形成层间绝缘层，并且层间绝缘层可以具有暴露半导体衬底的一部分的接触孔。 可以在接触孔中和在与半导体衬底相对的接触孔附近的层间绝缘层的部分上形成单晶半导体插塞，并且与半导体衬底相对的部分层间绝缘层可以不含单晶半导体插头。 可以去除接触孔中的单晶半导体插塞的部分，同时将单晶半导体插塞的部分保持在与接触孔相邻的层间绝缘层的部分上作为单晶半导体接触图案。 在去除单晶半导体插头的部分之后，可以在层间绝缘层和单晶半导体接触图案上形成单晶半导体层。 可以在单晶半导体层上形成第二层间绝缘层，并且可以通过单晶半导体层通过第二层间绝缘层形成公共接触孔，并且通过第一层间绝缘层暴露半导体的一部分 基质。 此外，可以在与半导体衬底接触的公共接触孔中形成导电接触插塞。 还讨论了相关设备。