公开(公告)号：US08059234B2

公开(公告)日：2011-11-15

申请号：US12017176

申请日：2008-01-21

Applicant: Chun-Chieh Tsao ,  Hsiang-Lin Lin

Inventor： Chun-Chieh Tsao ,  Hsiang-Lin Lin

IPC: G02F1/1335

CPC classification number: G02F1/133516 ,  G02F1/133512

Abstract: A color filter and a black matrix thereof are provided. The black matrix disposed on the substrate comprises a frame that defines a pixel area for accommodating color filter inks when performing the ink-jet process, and a spacer disposed in each of the pixels for preventing inks from overflowing to adjacent pixel areas and improving the flatness of the formed color filter layer.

Abstract translation: 提供滤色器及其黑矩阵。 设置在基板上的黑色矩阵包括框架，该框架在执行喷墨处理时限定用于容纳滤色器墨水的像素区域，以及设置在每个像素中的间隔物，用于防止墨水溢出到相邻像素区域并提高平坦度 形成的滤色器层。

公开(公告)号：US20110263053A1

公开(公告)日：2011-10-27

申请号：US13174795

申请日：2011-07-01

Applicant: Hsiang-Lin Lin ,  Ching-Yu Tsai ,  Yi-Sheng Cheng ,  Kuo-Yu Huang

Inventor： Hsiang-Lin Lin ,  Ching-Yu Tsai ,  Yi-Sheng Cheng ,  Kuo-Yu Huang

IPC: H01L33/00

CPC classification number: H01L27/1288 ,  G09G3/3648 ,  G09G2300/0465 ,  H01L27/124 ,  H01L27/1255 ,  H01L29/0657 ,  H01L29/41733 ,  H01L29/42384

Abstract: A pixel structure including a scan line, a data line, an active device, a shielding electrode, and a pixel electrode is provided on a substrate. The data line includes an upper conductive wire and a bottom conductive wire. The upper conductive wire is disposed over and across the scan line. The bottom conductive wire is electrically connected to the upper conductive wire. The active device is electrically connected to the scan line and the upper conductive wire. The shielding electrode is disposed over the bottom conductive wire. The pixel electrode disposed over the shielding electrode is electrically connected to the active device. In addition, parts of the pixel electrode and parts of the shielding electrode form a storage capacitor.

Abstract translation: 在基板上设置包括扫描线，数据线，有源器件，屏蔽电极和像素电极的像素结构。 数据线包括上导线和底导线。 上导线设置在扫描线上方并穿过扫描线。 底部导线与上导电线电连接。 有源器件电连接到扫描线和上导电线。 屏蔽电极设置在底部导线上。 设置在屏蔽电极上方的像素电极与有源器件电连接。 此外，像素电极的一部分和屏蔽电极的一部分形成存储电容器。

公开(公告)号：US20110241009A1

公开(公告)日：2011-10-06

申请号：US13163780

申请日：2011-06-20

Applicant: Kuo-Lung Fang ,  Hsiang-Lin Lin ,  Chin-Yueh Liao

Inventor： Kuo-Lung Fang ,  Hsiang-Lin Lin ,  Chin-Yueh Liao

IPC: H01L27/06

CPC classification number: H01L29/458 ,  H01L27/124 ,  H01L27/1288

Abstract: A pixel structure includes a scan line, a data line, an active element, a first passivation layer, a second passivation layer and a pixel electrode. The data line includes a first data metal segment and a second data metal layer. The active element includes a gate electrode, an insulating layer, a channel layer, a source and a drain. The channel layer is positioned on the insulating layer above the gate electrode. The source and the drain are positioned on the channel layer. The source is coupled to the data line. The first passivation layer and the second passivation layer cover the active element and form a first contact hole to expose a part of the drain. The second passivation layer covers a part edge of the drain. The pixel electrode is disposed across the second passivation layer and coupled to the drain via the first contact hole.

Abstract translation: 像素结构包括扫描线，数据线，有源元件，第一钝化层，第二钝化层和像素电极。 数据线包括第一数据金属段和第二数据金属层。 有源元件包括栅电极，绝缘层，沟道层，源极和漏极。 沟道层位于栅电极上方的绝缘层上。 源极和漏极位于沟道层上。 源耦合到数据线。 第一钝化层和第二钝化层覆盖有源元件并形成第一接触孔以暴露漏极的一部分。 第二钝化层覆盖漏极的一部分边缘。 像素电极跨越第二钝化层设置并且经由第一接触孔耦合到漏极。

公开(公告)号：US07855382B2

公开(公告)日：2010-12-21

申请号：US12725458

申请日：2010-03-17

Applicant: Hsiang-Lin Lin ,  Chun-Chieh Tsao

Inventor： Hsiang-Lin Lin ,  Chun-Chieh Tsao

IPC: H01L29/04 ,  H01L31/036 ,  H01L31/0376 ,  H01L31/20

CPC classification number: G02F1/133555 ,  G02F1/136227 ,  H01L27/124 ,  H01L27/1248

Abstract: A pixel structure including a gate, a gate dielectric layer, a patterned semiconductor layer having a channel area disposed above the gate, a patterned dielectric layer having an etching-stop layer disposed above the gate and a number of bumps, a patterned metal layer having a reflective pixel electrode, a source and a drain, an overcoat dielectric layer, and a transparent pixel electrode sequentially disposed on a substrate is provided. The source and the drain respectively cover portions of the channel area. The reflective pixel electrode connects the drain and covers the bumps to form an uneven surface. The overcoat dielectric layer disposed on a transistor constituted by the gate, the gate dielectric layer, the patterned semiconductor layer, the source and the drain has a contact opening exposing a portion of the reflective pixel electrode. The transparent pixel electrode is electrically connected to the reflective pixel electrode through the contact opening.

Abstract translation: 一种像素结构，包括栅极，栅极电介质层，具有设置在栅极上方的沟道区域的图案化半导体层，具有设置在栅极上方的蚀刻停止层和多个凸起的图案化电介质层，具有 提供反射像素电极，源极和漏极，外涂层电介质层和顺序地设置在基板上的透明像素电极。 源极和漏极分别覆盖沟道区域的部分。 反射像素电极连接漏极并覆盖凸块以形成不平坦的表面。 设置在由栅极，栅极电介质层，图案化半导体层，源极和漏极构成的晶体管上的外涂层电介质层具有暴露反射像素电极的一部分的接触开口。 透明像素电极通过接触开口电连接到反射像素电极。

公开(公告)号：US07816193B2

公开(公告)日：2010-10-19

申请号：US11964758

申请日：2007-12-27

Applicant: Hsiang-Lin Lin

Inventor： Hsiang-Lin Lin

IPC: H01L21/84

CPC classification number: H01L27/1248 ,  G02F2001/136231 ,  H01L27/1288 ,  H01L51/56 ,  H01L2227/323 ,  Y10S438/958

Abstract: A method for fabricating a pixel structure of a liquid crystal device is provided. The method comprises providing a substrate defining a thin film transistor (TFT) region and a display region thereon. An opaque conductive layer is formed on the TFT region, and a transparent pixel electrode is formed on the display region. A patterned photoresist passivation layer is formed by backside exposure process on the TFT region, wherein the opaque conductive layer serves as the photo-mask during the backside exposure process. The photoresist passivation layer is subjected to a middle bake process to be reflowed, resulting in a complete covering of the opaque conductive layer.

Abstract translation: 提供一种用于制造液晶装置的像素结构的方法。 该方法包括提供限定薄膜晶体管（TFT）区域的基板和其上的显示区域。 在TFT区域上形成不透明导电层，在显示区域上形成透明像素电极。 在TFT区域上通过背面曝光工艺形成图案化的光致抗蚀剂钝化层，其中不透明导电层在背面曝光工艺期间用作光掩模。 对光致抗蚀剂钝化层进行中间烘烤处理以回流，导致不透明导电层的完全覆盖。

公开(公告)号：US20100259701A1

公开(公告)日：2010-10-14

申请号：US12508573

申请日：2009-07-24

Applicant: Ching-Huan Lin ,  Hsiang-Lin Lin ,  Shih-Chia Hsu ,  Sheng-Chao Liu ,  Kuang-Hsiang Liu

Inventor： Ching-Huan Lin ,  Hsiang-Lin Lin ,  Shih-Chia Hsu ,  Sheng-Chao Liu ,  Kuang-Hsiang Liu

IPC: G02F1/1343

CPC classification number: G02F1/136286 ,  G09G3/3655 ,  G09G2300/0456 ,  G09G2320/0673

Abstract: A liquid crystal display (LCD) is provided. The LCD includes a display panel and a voltage supply device (VSD). The display panel includes a plurality of scan lines, a plurality of data lines disposed substantially perpendicularly with the scan lines, and a plurality of pixels. The pixels are respectively electrically connected with the corresponding data line and the corresponding scan line, and are arranged in an array. Each of the pixels includes a common line and a compensation line, wherein the common line is located in the transparent area to receive a common voltage, and the compensation line is located in the reflection area to receive a stable voltage. The VSD is coupled to the compensation line of each of the pixels for continuously and correspondingly providing the stable voltage to the compensation line of each of the pixels.

Abstract translation: 提供液晶显示器（LCD）。 LCD包括显示面板和电压供应装置（VSD）。 显示面板包括多条扫描线，与扫描线大致垂直设置的多条数据线以及多个像素。 像素分别与相应的数据线和对应的扫描线电连接，并且被排列成阵列。 每个像素包括公共线和补偿线，其中公共线位于透明区域中以接收公共电压，并且补偿线位于反射区域中以接收稳定的电压。 VSD耦合到每个像素的补偿线，用于连续地并相应地将稳定的电压提供给每个像素的补偿线。

公开(公告)号：US20100187537A1

公开(公告)日：2010-07-29

申请号：US12436221

申请日：2009-05-06

Applicant: Hsiang-Lin Lin

Inventor： Hsiang-Lin Lin

IPC: H01L29/786 ,  H01L33/00 ,  H01L21/336

CPC classification number: H01L27/124 ,  H01L27/1248 ,  H01L27/1288

Abstract: A thin film transistor array structure and a method for manufacturing the same are provided. The thin film transistor array structure comprises a substrate, including a transition area and a pad area. A patterned first metal layer is formed on the substrate, wherein the patterned first metal layer includes a data connecting line disposed in the transition area, and a data pad and a gate pad disposed in the pad area. A patterned first insulation layer is formed on the patterned first metal layer. The patterned first insulation layer at least defines a first opening on the gate pad, a second opening on the data pad, and a third opening in the transition area, so as to simplify following processes to increase the yield.

Abstract translation: 提供薄膜晶体管阵列结构及其制造方法。 薄膜晶体管阵列结构包括基板，其包括过渡区域和焊盘区域。 图案化的第一金属层形成在基板上，其中图案化的第一金属层包括设置在过渡区域中的数据连接线，以及设置在焊盘区域中的数据焊盘和栅极焊盘。 图案化的第一绝缘层形成在图案化的第一金属层上。 图案化的第一绝缘层至少限定了栅极焊盘上的第一开口，数据焊盘上的第二开口和过渡区域中的第三开口，以便简化后续处理以提高产量。

公开(公告)号：US07705950B2

公开(公告)日：2010-04-27

申请号：US11382059

申请日：2006-05-08

Applicant: Hsiang-Lin Lin

Inventor： Hsiang-Lin Lin

IPC: G02F1/1343

CPC classification number: G02F1/134309 ,  G02F1/136213 ,  G02F1/136286 ,  G02F2001/13606

Abstract: A liquid crystal display includes: a substrate; a plurality of pixel electrodes formed on the substrate and arranged corresponding to a pixel array; a first data line and a second data line formed on the substrate; a plurality of scan lines formed on the substrate, in which the scan lines cross the first data line and the second data line; a first branch electrode electrically connects a pixel electrode and partially overlaps the first data line; and a second branch electrode electrically connects the pixel electrode and partially overlaps the second data line, in which the first branch electrode and the second branch electrode are disposed opposite to the pixel electrode.

Abstract translation: 液晶显示器包括：基板; 多个像素电极，其形成在所述基板上并且对应于像素阵列排列; 形成在所述基板上的第一数据线和第二数据线; 形成在所述基板上的扫描线，其中所述扫描线与所述第一数据线和所述第二数据线交叉; 第一分支电极电连接像素电极并与第一数据线部分重叠; 并且第二分支电极电连接像素电极，并且与第二数据线部分重叠，其中第一分支电极和第二分支电极与像素电极相对设置。

公开(公告)号：US20100059758A1

公开(公告)日：2010-03-11

申请号：US12405247

申请日：2009-03-17

Applicant: Sheng-Chao Liu ,  Hsiang-Lin Lin ,  Kuang-Hsiang Liu ,  Ching-Huan Lin ,  Ming-Tien Lin

Inventor： Sheng-Chao Liu ,  Hsiang-Lin Lin ,  Kuang-Hsiang Liu ,  Ching-Huan Lin ,  Ming-Tien Lin

IPC: H01L33/00 ,  H01L29/786

CPC classification number: H01L27/1255 ,  G02F1/136286 ,  H01L27/1214

Abstract: A tri-gate pixel structure includes three sub-pixel regions, three gate lines, a data line, three thin film transistors (TFTs), three pixel electrodes, and a common line. The gate lines are disposed along a first direction, and the data line is disposed along a second direction. The TFTs are disposed in the sub-pixel regions respectively, wherein each TFT has a gate electrode electrically connected to a corresponding gate line, a source electrode electrically connected to the data line, and a drain electrode. The three pixel electrodes are disposed in the three sub-pixel regions respectively, and each pixel electrode is electrically connected to the drain electrode of one TFT respectively. The common line crosses the gate lines and partially overlaps the three gate lines, and the common line and the three pixel electrodes are partially overlapped to respectively form three storage capacitors.

Abstract translation: 三栅极像素结构包括三个子像素区域，三个栅极线，数据线，三个薄膜晶体管（TFT），三个像素电极和公共线。 栅极线沿着第一方向设置，并且数据线沿着第二方向设置。 TFT分别设置在子像素区域中，其中每个TFT具有电连接到相应的栅极线的栅电极，与数据线电连接的源电极和漏电极。 三个像素电极分别设置在三个子像素区域中，并且每个像素电极分别电连接到一个TFT的漏电极。 公共线与栅极线交叉并且部分地重叠三条栅极线，并且公共线和三个像素电极部分地重叠以分别形成三个存储电容器。

公开(公告)号：US20090256164A1

公开(公告)日：2009-10-15

申请号：US12190887

申请日：2008-08-13

Applicant: Kuo-Lung Fang ,  Hsiang-Lin Lin ,  Han-Tu Lin

Inventor： Kuo-Lung Fang ,  Hsiang-Lin Lin ,  Han-Tu Lin

IPC: H01L33/00 ,  H01L21/30

CPC classification number: H01L27/1288 ,  H01L27/124

Abstract: An active device array substrate and its fabricating method are provided. According to the subject invention, the elements of an array substrate such as the thin film transistors, gate lines, gate pads, data lines, data pads and storage electrodes, are provided by forming a patterned first metal layer, an insulating layer, a patterned semiconductor layer and a patterned metal multilayer. Furthermore, the subject invention uses the means of selectively etching certain layers. Using the aforesaid means, the array substrate of the subject invention has some layers with under-cut structures, and thus, the number of the time-consuming and complicated mask etching process involved in the production of an array substrate can be reduced. The subject invention provides a relatively simple and time-saving method for producing an array substrate.

Abstract translation: 提供一种有源器件阵列衬底及其制造方法。 根据本发明，诸如薄膜晶体管，栅极线，栅极焊盘，数据线，数据焊盘和存储电极之类的阵列基板的元件通过形成图案化的第一金属层，绝缘层，图案化 半导体层和图案化金属多层。 此外，本发明使用选择性蚀刻某些层的方法。 使用上述方法，本发明的阵列基板具有一些具有欠切割结构的层，因此可以减少在阵列基板的制造中涉及的耗时且复杂的掩模蚀刻工艺的数量。 本发明提供了用于制造阵列基板的相对简单且省时的方法。