Abstract:
A flexible Ethernet (FlexE) frame forwarding method, including receiving a first frame through a FlexE client input channel, obtaining a first channel identifier used to indicate the FlexE client input channel and a first subchannel identifier carried in the first frame, where the first subchannel identifier is used to indicate a logical subchannel of the FlexE client input channel, searching a preset forwarding table based on the first channel identifier and the first subchannel identifier to obtain a second channel identifier and a second subchannel identifier, where the second channel identifier is used to indicate a FlexE client output channel, and the second subchannel identifier is used to indicate a logical subchannel of the FlexE client output channel, and forwarding the first frame based on the second channel identifier and the second subchannel identifier.
Abstract:
A clock synchronization method includes receiving, by a receiving apparatus, a plurality of data blocks using a plurality of physical layer modules (PHYs), where the plurality of data blocks include a plurality of head data blocks, performing, by the receiving apparatus, timestamp sampling on the plurality of data blocks to generate a plurality of receipt timestamps, aligning, by the receiving apparatus, the plurality of receipt timestamps using a first receipt timestamp as a reference, generating, by the receiving apparatus, a clock synchronization packet based on the plurality of data blocks, and writing, by the receiving apparatus, a value of a second receipt timestamp into the clock synchronization packet, where the second receipt timestamp is a receipt timestamp that is of a second data block and that is determined based on the plurality of aligned receipt timestamps.
Abstract:
A receiving-side chip is disclosed according to the present invention, which includes a processor, configured to acquire and execute following instructions: receiving link information sent by a sending-side chip, and enabling, according to the link information, a SerDes link to be added; receiving padding data from the added SerDes link according to a short unit frame period to acquire a synchronization word, and determining, according to the synchronization word, whether the added SerDes link has been synchronized; switching a read period of data in the added SerDes link from the short unit frame period into a long unit frame period, and aligning the data of the added SerDes link with the data of an original SerDes link; and receiving service data over the added SerDes link and the original SerDes link.
Abstract:
Embodiments of the present invention provide a bandwidth adjustment method, a bus controller, and a signal convertor. The method includes: obtaining, by a bus controller, a first frequency and a first channel number; sending a bandwidth negotiation request carrying the first frequency and the first channel number to a bus controller of a first peer end to determine whether or not the bus controller of the first peer end is capable of controlling a physical component of the first peer end to receive data via a channel corresponding to the first channel number according to the first frequency; and receiving a negotiation result sent by the first peer end and controlling the physical component to transmit data according to the negotiation result. In the technical solutions of the embodiments of the present invention, bandwidth adjustment is flexible and the loss of data is avoided.
Abstract:
Embodiments of this application disclose a synchronization method and a device. A device marks, based on a preset period, a periodic code block in a data bitstream to be sent from a MAC layer to a PHY layer. The device sends the data bitstream to a peer device through the PHY layer, records a sending time of each periodic code block as a first timestamp during sending, and returns the first timestamp to the MAC layer. By marking a timestamp for the periodic code block received from the MAC layer, the device sets a PHY-layer-based time reference scale (namely, the first timestamp) at the PHY layer.
Abstract:
This disclosure provides a method for sending and receiving a clock synchronization packet in FlexE. The method includes: generating, by a sending apparatus, indication information and a plurality of data blocks, where the plurality of data blocks are obtained by encoding a first clock synchronization packet, the indication information is used to indicate a first data block, and the first data block is a data block used for timestamp sampling in the plurality of data blocks; determining, by the sending apparatus, according to the indication information, a moment at which the first data block arrives at a medium dependent interface MDI of the sending apparatus, and generating a sending timestamp, where the sending timestamp is used to record a sending moment of the first clock synchronization packet; generating a second clock synchronization packet carrying the sending timestamp; and sending, by the sending apparatus, the second clock synchronization packet.
Abstract:
A clock synchronization method includes receiving, by a receiving apparatus, a plurality of data blocks using a plurality of physical layer modules (PHYs), where the plurality of data blocks include a plurality of head data blocks, performing, by the receiving apparatus, timestamp sampling on the plurality of data blocks to generate a plurality of receipt timestamps, aligning, by the receiving apparatus, the plurality of receipt timestamps using a first receipt timestamp as a reference, generating, by the receiving apparatus, a clock synchronization packet based on the plurality of data blocks, and writing, by the receiving apparatus, a value of a second receipt timestamp into the clock synchronization packet, where the second receipt timestamp is a receipt timestamp that is of a second data block and that is determined based on the plurality of aligned receipt timestamps.
Abstract:
A clock synchronization method includes receiving, by a receiving apparatus, a plurality of data blocks using a plurality of physical layer modules (PHYs), where the plurality of data blocks include a plurality of head data blocks, performing, by the receiving apparatus, timestamp sampling on the plurality of data blocks to generate a plurality of receipt timestamps, aligning, by the receiving apparatus, the plurality of receipt timestamps using a first receipt timestamp as a reference, generating, by the receiving apparatus, a clock synchronization packet based on the plurality of data blocks, and writing, by the receiving apparatus, a value of a second receipt timestamp into the clock synchronization packet, where the second receipt timestamp is a receipt timestamp that is of a second data block and that is determined based on the plurality of aligned receipt timestamps.
Abstract:
A terminal with a line-of-sight tracking function is disclosed. The terminal with a line-of-sight tracking function includes a body, a camera, and at least two light emitting diodes. The camera and the at least two light emitting diodes are mounted on the body, so that the terminal can emit a ray by using the at least two light emitting diodes, to ensure that the emitted ray can be shined on an eye of the user when the user is at different angles. After the ray is reflected by the eye of the user, the terminal can collect the reflected ray by using the camera, obtain an eye image of the user, and track a line of sight of the user based on the eye image, thereby increasing a success rate of line-of-sight tracking.
Abstract:
A projection apparatus includes a projection cavity, a light source, a scanning motor, and a processor. The light source and the scanning motor are located inside the projection cavity, and the processor is connected to both the light source and the scanning motor. A reflection layer is disposed on a scanning mirror of the scanning motor, where the reflection layer is configured to reflect light emitted by the light source.