Flexible ethernet frame forwarding method and apparatus

    公开(公告)号:US11206216B2

    公开(公告)日:2021-12-21

    申请号:US16851615

    申请日:2020-04-17

    Abstract: A flexible Ethernet (FlexE) frame forwarding method, including receiving a first frame through a FlexE client input channel, obtaining a first channel identifier used to indicate the FlexE client input channel and a first subchannel identifier carried in the first frame, where the first subchannel identifier is used to indicate a logical subchannel of the FlexE client input channel, searching a preset forwarding table based on the first channel identifier and the first subchannel identifier to obtain a second channel identifier and a second subchannel identifier, where the second channel identifier is used to indicate a FlexE client output channel, and the second subchannel identifier is used to indicate a logical subchannel of the FlexE client output channel, and forwarding the first frame based on the second channel identifier and the second subchannel identifier.

    Clock synchronization method and apparatus

    公开(公告)号:US11108485B2

    公开(公告)日:2021-08-31

    申请号:US16860688

    申请日:2020-04-28

    Abstract: A clock synchronization method includes receiving, by a receiving apparatus, a plurality of data blocks using a plurality of physical layer modules (PHYs), where the plurality of data blocks include a plurality of head data blocks, performing, by the receiving apparatus, timestamp sampling on the plurality of data blocks to generate a plurality of receipt timestamps, aligning, by the receiving apparatus, the plurality of receipt timestamps using a first receipt timestamp as a reference, generating, by the receiving apparatus, a clock synchronization packet based on the plurality of data blocks, and writing, by the receiving apparatus, a value of a second receipt timestamp into the clock synchronization packet, where the second receipt timestamp is a receipt timestamp that is of a second data block and that is determined based on the plurality of aligned receipt timestamps.

    Dynamic link adjustment method and link managing device
    23.
    发明授权
    Dynamic link adjustment method and link managing device 有权
    动态链路调整方法和链路管理设备

    公开(公告)号:US09014214B2

    公开(公告)日:2015-04-21

    申请号:US13961423

    申请日:2013-08-07

    CPC classification number: H04J3/0605 H04L7/10 H04L25/14

    Abstract: A receiving-side chip is disclosed according to the present invention, which includes a processor, configured to acquire and execute following instructions: receiving link information sent by a sending-side chip, and enabling, according to the link information, a SerDes link to be added; receiving padding data from the added SerDes link according to a short unit frame period to acquire a synchronization word, and determining, according to the synchronization word, whether the added SerDes link has been synchronized; switching a read period of data in the added SerDes link from the short unit frame period into a long unit frame period, and aligning the data of the added SerDes link with the data of an original SerDes link; and receiving service data over the added SerDes link and the original SerDes link.

    Abstract translation: 根据本发明公开了一种根据本发明的接收侧芯片,其包括:处理器,被配置为获取和执行以下指令:接收由发送侧芯片发送的链路信息,并且根据链路信息使得能够将SerDes链路 被添加 根据短单位帧周期从所添加的SerDes链路接收填充数据以获取同步字,并根据所述同步字确定添加的SerDes链路是否已被同步; 将添加的SerDes链路中的数据的读取周期从短单位帧周期切换到长单位帧周期,并且将所添加的SerDes链路的数据与原始SerDes链路的数据对齐; 并通过添加的SerDes链接和原始SerDes链接接收服务数据。

    BANDWIDTH ADJUSTMENT METHOD, BUS CONTROLLER, AND SIGNAL CONVERTOR
    24.
    发明申请
    BANDWIDTH ADJUSTMENT METHOD, BUS CONTROLLER, AND SIGNAL CONVERTOR 有权
    带宽调整方法,总线控制器和信号转换器

    公开(公告)号:US20140016651A1

    公开(公告)日:2014-01-16

    申请号:US14027931

    申请日:2013-09-16

    CPC classification number: H04L47/76 G06F13/4295

    Abstract: Embodiments of the present invention provide a bandwidth adjustment method, a bus controller, and a signal convertor. The method includes: obtaining, by a bus controller, a first frequency and a first channel number; sending a bandwidth negotiation request carrying the first frequency and the first channel number to a bus controller of a first peer end to determine whether or not the bus controller of the first peer end is capable of controlling a physical component of the first peer end to receive data via a channel corresponding to the first channel number according to the first frequency; and receiving a negotiation result sent by the first peer end and controlling the physical component to transmit data according to the negotiation result. In the technical solutions of the embodiments of the present invention, bandwidth adjustment is flexible and the loss of data is avoided.

    Abstract translation: 本发明的实施例提供一种带宽调整方法,总线控制器和信号转换器。 该方法包括:由总线控制器获得第一频率和第一频道号码; 向第一对端的总线控制器发送携带第一频率和第一频道号的带宽协商请求,以确定第一对等端的总线控制器是否能够控制第一对等端的物理组件接收 经由与第一频道号对应的频道的数据,根据第一频率; 以及接收由所述第一对等端发送的协商结果,并根据所述协商结果控制所述物理组件发送数据。 在本发明的实施例的技术方案中,带宽调整是灵活的,并且避免了数据丢失。

    Synchronization method and device
    25.
    发明授权

    公开(公告)号:US12133185B2

    公开(公告)日:2024-10-29

    申请号:US17725962

    申请日:2022-04-21

    CPC classification number: H04W56/001 H04J3/0667 H04W80/02

    Abstract: Embodiments of this application disclose a synchronization method and a device. A device marks, based on a preset period, a periodic code block in a data bitstream to be sent from a MAC layer to a PHY layer. The device sends the data bitstream to a peer device through the PHY layer, records a sending time of each periodic code block as a first timestamp during sending, and returns the first timestamp to the MAC layer. By marking a timestamp for the periodic code block received from the MAC layer, the device sets a PHY-layer-based time reference scale (namely, the first timestamp) at the PHY layer.

    METHOD AND APPARATUS FOR SENDING AND RECEIVING CLOCK SYNCHRONIZATION PACKET

    公开(公告)号:US20220303035A1

    公开(公告)日:2022-09-22

    申请号:US17833862

    申请日:2022-06-06

    Abstract: This disclosure provides a method for sending and receiving a clock synchronization packet in FlexE. The method includes: generating, by a sending apparatus, indication information and a plurality of data blocks, where the plurality of data blocks are obtained by encoding a first clock synchronization packet, the indication information is used to indicate a first data block, and the first data block is a data block used for timestamp sampling in the plurality of data blocks; determining, by the sending apparatus, according to the indication information, a moment at which the first data block arrives at a medium dependent interface MDI of the sending apparatus, and generating a sending timestamp, where the sending timestamp is used to record a sending moment of the first clock synchronization packet; generating a second clock synchronization packet carrying the sending timestamp; and sending, by the sending apparatus, the second clock synchronization packet.

    Clock Synchronization Method and Apparatus

    公开(公告)号:US20210376943A1

    公开(公告)日:2021-12-02

    申请号:US17403131

    申请日:2021-08-16

    Abstract: A clock synchronization method includes receiving, by a receiving apparatus, a plurality of data blocks using a plurality of physical layer modules (PHYs), where the plurality of data blocks include a plurality of head data blocks, performing, by the receiving apparatus, timestamp sampling on the plurality of data blocks to generate a plurality of receipt timestamps, aligning, by the receiving apparatus, the plurality of receipt timestamps using a first receipt timestamp as a reference, generating, by the receiving apparatus, a clock synchronization packet based on the plurality of data blocks, and writing, by the receiving apparatus, a value of a second receipt timestamp into the clock synchronization packet, where the second receipt timestamp is a receipt timestamp that is of a second data block and that is determined based on the plurality of aligned receipt timestamps.

    Clock Synchronization Method and Apparatus
    28.
    发明申请

    公开(公告)号:US20200259578A1

    公开(公告)日:2020-08-13

    申请号:US16860688

    申请日:2020-04-28

    Abstract: A clock synchronization method includes receiving, by a receiving apparatus, a plurality of data blocks using a plurality of physical layer modules (PHYs), where the plurality of data blocks include a plurality of head data blocks, performing, by the receiving apparatus, timestamp sampling on the plurality of data blocks to generate a plurality of receipt timestamps, aligning, by the receiving apparatus, the plurality of receipt timestamps using a first receipt timestamp as a reference, generating, by the receiving apparatus, a clock synchronization packet based on the plurality of data blocks, and writing, by the receiving apparatus, a value of a second receipt timestamp into the clock synchronization packet, where the second receipt timestamp is a receipt timestamp that is of a second data block and that is determined based on the plurality of aligned receipt timestamps.

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