公开(公告)号：US20180342524A1

公开(公告)日：2018-11-29

申请号：US15980604

申请日：2018-05-15

Applicant: IMEC VZW

Inventor： Julien Ryckaert ,  Naoto Horiguchi ,  Dan Mocuta ,  Trong Huynh Bao

IPC: H01L27/11 ,  H01L27/092 ,  H01L29/15 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/1104 ,  H01L21/823431 ,  H01L21/823487 ,  H01L21/823885 ,  H01L27/0886 ,  H01L27/092 ,  H01L29/41741 ,  H01L29/66666 ,  H01L29/66787 ,  H01L29/7827 ,  H01L29/785 ,  H01L29/78642 ,  H01L2029/7858

Abstract: The disclosed technology generally relates semiconductor devices and more particularly to a vertical transistor device, and a method of fabricating the same. In one aspect, the method includes providing, on a substrate, a fin formed of a stack of a first layer, a second layer and a third layer, wherein the second layer is positioned above the first layer and the third layer is positioned above the second layer. The method additionally includes forming a dielectric on the sidewalls of the first and third layers of the fin selectively against a sidewall of the second layer, and the method additionally includes forming a gate contacting layer for contacting a sidewall of the second layer. The first and third layers define a source region and a drain region, respectively, of the vertical transistor device. The second layer defines a channel region of the vertical transistor device. The dielectric on the sidewalls of the first and third layers electrically isolates the source and drain regions from the gate contacting layer.

公开(公告)号：US20180174644A1

公开(公告)日：2018-06-21

申请号：US15833802

申请日：2017-12-06

Applicant: IMEC VZW ,  VRIJE UNIVERSITEIT BRUSSEL ,  Katholieke Universiteit Leuven, KU LEUVEN R&D

Inventor： Sushil Sakhare ,  Trong Huynh Bao ,  Manu Komalan Perumkunnil

IPC: G11C11/417 ,  G11C13/00

CPC classification number: G11C11/417 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/4125 ,  G11C11/419 ,  G11C13/0038 ,  G11C14/0081 ,  G11C14/009

Abstract: A memory cell is disclosed, comprising a static random-access memory, SRAM, bit cell, a first resistive memory element and a second resistive memory element. The first resistive memory element is connected to a first storage node of the SRAM bit cell and a first intermediate node, and the second resistive memory element connected to a second storage node of the SRAM bit cell and a second intermediate node. Each one of the first intermediate node and the second intermediate node is configured to be supplied with a first supply voltage via a first transistor and a second supply voltage via a second transistor, wherein the first transistor and the second transistor are complementary transistors separately controllable by a first word line and a second word line, respectively. Methods for operating such a memory cell are also disclosed.

公开(公告)号：US20170358586A1

公开(公告)日：2017-12-14

申请号：US15349904

申请日：2016-11-11

Applicant: IMEC VZW ,  Vrije Universiteit Brussel

Inventor： Trong Huynh Bao ,  Anabela Veloso ,  Julien Ryckaert

IPC: H01L27/11 ,  H01L29/423 ,  H01L23/528 ,  H01L29/06 ,  H01L29/786 ,  H01L29/417 ,  H01L29/10

CPC classification number: H01L29/42392 ,  B82Y10/00 ,  H01L27/0688 ,  H01L27/1104 ,  H01L29/0676 ,  H01L29/41733 ,  H01L29/66439 ,  H01L29/66666 ,  H01L29/775 ,  H01L29/78642 ,  H01L29/7869

Abstract: The disclosed technology generally relates to semiconductor devices, and more particularly to semiconductor devices having a stacked arrangement, and further relates to methods of fabricating such devices. In one aspect, a semiconductor device comprises a first memory device and a second memory device formed over a substrate and at least partly stacked in a vertical direction. Each of the first and second memory devices has a plurality of vertical transistors, wherein each vertical transistor has a vertical channel extending in the vertical direction.