公开(公告)号：US20220246608A1

公开(公告)日：2022-08-04

申请号：US17726412

申请日：2022-04-21

Applicant: Intel Corporation

Inventor： Aaron D. LILAK ,  Anh PHAN ,  Ehren MANNEBACH ,  Cheng-Ying HUANG ,  Stephanie A. BOJARSKI ,  Gilbert DEWEY ,  Orb ACTON ,  Willy RACHMADY

IPC: H01L27/088 ,  H01L29/423 ,  H01L29/08 ,  H01L21/762 ,  H01L23/528 ,  H01L29/78 ,  H01L29/06

Abstract: Stacked transistor structures having a conductive interconnect between upper and lower transistors. In an embodiment, the interconnect is formed by first provisioning a protective layer over an area to be protected (gate dielectric or other sensitive material) of upper transistor, and then etching material adjacent and below the protected area to expose an underlying contact point of lower transistor. A metal is deposited into the void created by the etch to provide the interconnect. The protective layer is resistant to the etch process and is preserved in the structure, and in some cases may be utilized as a work-function metal. In an embodiment, the protective layer is formed by deposition of reactive semiconductor and metal material layers which are subsequently transformed into a work function metal or work function metal-containing compound. A remnant of unreacted reactive semiconductor material may be left in structure and collinear with protective layer.

公开(公告)号：US20220069094A1

公开(公告)日：2022-03-03

申请号：US17522764

申请日：2021-11-09

Applicant: Intel Corporation

Inventor： Patrick MORROW ,  Rishabh MEHANDRU ,  Aaron D. LILAK ,  Kimin JUN

IPC: H01L29/417 ,  H01L29/423 ,  H01L27/12 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/40

Abstract: An apparatus including a circuit structure including a device stratum including a plurality of devices including a first side and an opposite second side; and a metal interconnect coupled to at least one of the plurality of devices from the second side of the device stratum. A method including forming a transistor device including a channel between a source region and a drain region and a gate electrode on the channel defining a first side of the device; and forming an interconnect to one of the source region and the drain region from a second side of the device.

公开(公告)号：US20200176482A1

公开(公告)日：2020-06-04

申请号：US16785986

申请日：2020-02-10

Applicant: Intel Corporation

Inventor： Aaron D. LILAK ,  Patrick MORROW ,  Stephen M. CEA ,  Rishabh MEHANDRU ,  Cory E. WEBER

IPC: H01L27/12 ,  H01L29/78 ,  H01L21/265 ,  H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/3115 ,  H01L21/84

Abstract: Embodiments of the present invention are directed to formation of fins with different active channel heights in a tri-gate or a Fin-FET device. In an embodiment, at least two fins are formed on a front side of the substrate. A gate structure extends over a top surface and a pair of sidewalls of at least a portion of the fins. In an embodiment, the substrate is thinned to expose the bottom surface of the fins. Next, backside etching may be performed on each fin to form active channel regions. The fins may be recessed to different depths, forming active channel regions with differing heights.

公开(公告)号：US20230132053A1

公开(公告)日：2023-04-27

申请号：US18087129

申请日：2022-12-22

Applicant: Intel Corporation

Inventor： Aaron D. LILAK ,  Rishabh MEHANDRU ,  Patrick MORROW

IPC: H01L21/762 ,  H01L21/8234 ,  H01L27/12

Abstract: Techniques are disclosed for forming integrated circuit structures having a plurality of non-planar transistors. An insulation structure is provided between channel, source, and drain regions of neighboring fins. The insulation structure is formed during back side processing, wherein at least a first portion of the isolation material between adjacent fins is recessed to expose a sub-channel portion of the semiconductor fins. A spacer material is then deposited at least on the exposed opposing sidewalls of the exposed sub-channel portion of each fin. The isolation material is then further recessed to form an air gap between gate, source, and drain regions of neighboring fins. The air gap electrically isolates the source/drain regions of one fin from the source/drain regions of an adjacent fin, and likewise isolates the gate region of the one fin from the gate region of the adjacent fin. The air gap can be filled with a dielectric material.

公开(公告)号：US20230095007A1

公开(公告)日：2023-03-30

申请号：US17485173

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Rishabh MEHANDRU ,  Stephen M. CEA ,  Aaron D. LILAK ,  Cory WEBER ,  Patrick KEYS ,  Navid PAYDAVOSI

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/786

Abstract: Integrated circuit structures having metal-containing source or drain structures, and methods of fabricating integrated circuit structures having metal-containing source or drain structures, are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires, and a second epitaxial source or drain structure is at a second end of the vertical arrangement of horizontal nanowires. The first and second epitaxial source or drain structures include a metal species diffused therein, the metal species further diffused partially into the vertical arrangement of horizontal nanowires.

公开(公告)号：US20220246743A1

公开(公告)日：2022-08-04

申请号：US17727603

申请日：2022-04-22

Applicant: Intel Corporation

Inventor： Aaron D. LILAK ,  Rishabh MEHANDRU ,  Cory WEBER ,  Willy RACHMADY ,  Varun MISHRA

IPC: H01L29/423 ,  H01L21/02 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/165 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

Abstract: Gate-all-around integrated circuit structures having an insulator fin on an insulator substrate, and methods of fabricating gate-all-around integrated circuit structures having an insulator fin on an insulator substrate, are described. For example, an integrated circuit structure includes an insulator fin on an insulator substrate. A vertical arrangement of horizontal semiconductor nanowires is over the insulator fin. A gate stack surrounds a channel region of the vertical arrangement of horizontal semiconductor nanowires, and the gate stack is overlying the insulator fin. A pair of epitaxial source or drain structures is at first and second ends of the vertical arrangement of horizontal semiconductor nanowires and at first and second ends of the insulator fin.

公开(公告)号：US20210305388A1

公开(公告)日：2021-09-30

申请号：US16833184

申请日：2020-03-27

Applicant: Intel Corporation

Inventor： Aaron D. LILAK ,  Rishabh MEHANDRU ,  Cory WEBER ,  Willy RACHMADY ,  Varun MISHRA

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L29/165 ,  H01L29/10 ,  H01L21/02

Abstract: Gate-all-around integrated circuit structures having an insulator fin on an insulator substrate, and methods of fabricating gate-all-around integrated circuit structures having an insulator fin on an insulator substrate, are described. For example, an integrated circuit structure includes an insulator fin on an insulator substrate. A vertical arrangement of horizontal semiconductor nanowires is over the insulator fin. A gate stack surrounds a channel region of the vertical arrangement of horizontal semiconductor nanowires, and the gate stack is overlying the insulator fin. A pair of epitaxial source or drain structures is at first and second ends of the vertical arrangement of horizontal semiconductor nanowires and at first and second ends of the insulator fin.

公开(公告)号：US20210296315A1

公开(公告)日：2021-09-23

申请号：US16827566

申请日：2020-03-23

Applicant: Intel Corporation

Inventor： Aaron D. LILAK ,  Rishabh MEHANDRU ,  Ehren MANNEBACH ,  Patrick MORROW ,  Willy RACHMADY

IPC: H01L27/092 ,  H01L29/10 ,  H01L23/498 ,  H01L23/528

Abstract: Embodiments disclosed herein include a semiconductor device. In an embodiment, the semiconductor device comprises a first transistor strata. The first transistor strata comprises a first backbone, a first transistor adjacent to a first edge of the first backbone, and a second transistor adjacent to a second edge of the first backbone. In an embodiment, the semiconductor device further comprises a second transistor strata over the first transistor strata. The second transistor strata comprises a second backbone, a third transistor adjacent to a first edge of the second backbone, and a fourth transistor adjacent to a second edge of the second backbone.

公开(公告)号：US20210091080A1

公开(公告)日：2021-03-25

申请号：US16772636

申请日：2018-03-28

Applicant: Intel Corporation

Inventor： Gilbert DEWEY ,  Ravi PILLARISETTY ,  Abhishek A. SHARMA ,  Aaron D. LILAK ,  Willy RACHMADY ,  Rishabh MEHANDRU ,  Kimin JUN ,  Anh PHAN ,  Hui Jae YOO ,  Patrick MORROW ,  Cheng-Ying HUANG

IPC: H01L27/092 ,  H01L27/12 ,  H01L21/8254

Abstract: An integrated circuit structure comprises a lower device layer that includes a first structure comprising a plurality of PMOS transistors. An upper device layer is formed on the lower device layer, wherein the upper device layer includes a second structure comprising a plurality of NMOS thin-film transistors (TFT).

公开(公告)号：US20200381525A1

公开(公告)日：2020-12-03

申请号：US16999508

申请日：2020-08-21

Applicant: Intel Corporation

Inventor： Patrick MORROW ,  Rishabh MEHANDRU ,  Aaron D. LILAK ,  Kimin JUN

IPC: H01L29/417 ,  H01L29/423 ,  H01L27/12 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/40

Abstract: An apparatus including a circuit structure including a device stratum including a plurality of devices including a first side and an opposite second side; and a metal interconnect coupled to at least one of the plurality of devices from the second side of the device stratum. A method including forming a transistor device including a channel between a source region and a drain region and a gate electrode on the channel defining a first side of the device; and forming an interconnect to one of the source region and the drain region from a second side of the device.