公开(公告)号：US20210074703A1

公开(公告)日：2021-03-11

申请号：US16772101

申请日：2018-03-22

Applicant: Intel Corporation

Inventor： Cory E. WEBER ,  Haorld W. KENNEL ,  Willy RACHMADY ,  Gilbert DEWEY

IPC: H01L27/092 ,  H01L27/12 ,  H01L21/8258

Abstract: Semiconductor nanowire devices having (111)-plane channel sidewalls and methods of fabricating semiconductor nanowire devices having (111)-plane channel sidewalls are described. For example, an integrated circuit structure includes a first semiconductor device including a plurality of vertically stacked nanowires disposed above a substrate, each of the nanowires comprising a discrete channel region having lateral sidewalls along a carrier transport direction. The integrated circuit structure also includes a second semiconductor device including a semiconductor fin disposed above the substrate, the semiconductor fin having a channel region with a top and side surfaces, the channel region having lateral sidewalls along a carrier transport direction.

公开(公告)号：US20180204932A1

公开(公告)日：2018-07-19

申请号：US15570965

申请日：2015-06-17

Applicant: Intel Corporation

Inventor： Rishabh MEHANDRU ,  Partick MORROW ,  Ranjith KUMAR ,  Cory E. WEBER ,  Seiyon KIM ,  Stephen M. CEA ,  Tahir GHANI

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/06 ,  H01L27/12 ,  H01L27/108

CPC classification number: H01L29/66795 ,  H01L21/8221 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0688 ,  H01L27/10826 ,  H01L27/1104 ,  H01L27/1211 ,  H01L29/78 ,  H01L29/785

Abstract: Vertical integration schemes and circuit elements architectures for area scaling of semiconductor devices are described. In an example, an inverter structure includes a semiconductor fin separated vertically into an upper region and a lower region. A first plurality of gate structures is included for controlling the upper region of the semiconductor fin. A second plurality of gate structures is included for controlling the lower region of the semiconductor fin. The second plurality of gate structures has a conductivity type opposite the conductivity type of the first plurality of gate structures.

公开(公告)号：US20180248005A1

公开(公告)日：2018-08-30

申请号：US15774952

申请日：2015-12-23

Applicant: Intel Corporation

Inventor： Aaron D. LILAK ,  Stephen M. CEA ,  Rishabh MEHANDRU ,  Cory E. WEBER

IPC: H01L29/10 ,  H01L29/167 ,  H01L29/78 ,  H01L21/304 ,  H01L21/306 ,  H01L21/265 ,  H01L21/324 ,  H01L29/66

CPC classification number: H01L29/1083 ,  H01L21/26513 ,  H01L21/26566 ,  H01L21/304 ,  H01L21/30625 ,  H01L21/324 ,  H01L29/167 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: Methods for doping a sub-fin region of a semiconductor structure include providing a semiconductor structure that comprises a substrate and a plurality of fins formed on the substrate, the plurality of fins having sub-fin regions adjacent to the substrate; removing the substrate to expose a portion of the sub-fin regions of the plurality of fins, and implanting a dopant material into the exposed portion of the sub-fin region. The method may also include performing an annealing process after the implantation such that the dopant becomes electrically active. The method may also include patterning the backside of the semiconductor structure. Devices constructed using the disclosed methods are also provided, and other embodiments are discussed.

公开(公告)号：US20200176482A1

公开(公告)日：2020-06-04

申请号：US16785986

申请日：2020-02-10

Applicant: Intel Corporation

Inventor： Aaron D. LILAK ,  Patrick MORROW ,  Stephen M. CEA ,  Rishabh MEHANDRU ,  Cory E. WEBER

IPC: H01L27/12 ,  H01L29/78 ,  H01L21/265 ,  H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/3115 ,  H01L21/84

Abstract: Embodiments of the present invention are directed to formation of fins with different active channel heights in a tri-gate or a Fin-FET device. In an embodiment, at least two fins are formed on a front side of the substrate. A gate structure extends over a top surface and a pair of sidewalls of at least a portion of the fins. In an embodiment, the substrate is thinned to expose the bottom surface of the fins. Next, backside etching may be performed on each fin to form active channel regions. The fins may be recessed to different depths, forming active channel regions with differing heights.

公开(公告)号：US20200035818A1

公开(公告)日：2020-01-30

申请号：US16592380

申请日：2019-10-03

Applicant: Intel Corporation

Inventor： Stephen M. CEA ,  Cory E. WEBER ,  Patrick H. KEYS ,  Seiyon KIM ,  Michael G. HAVERTY ,  Sadasivan SHANKAR

IPC: H01L29/775 ,  B82Y10/00 ,  H01L29/06 ,  H01L29/66 ,  H01L29/417 ,  H01L29/786 ,  H01L29/78

Abstract: Nanowire structures having wrap-around contacts are described. For example, a nanowire semiconductor device includes a nanowire disposed above a substrate. A channel region is disposed in the nanowire. The channel region has a length and a perimeter orthogonal to the length. A gate electrode stack surrounds the entire perimeter of the channel region. A pair of source and drain regions is disposed in the nanowire, on either side of the channel region. Each of the source and drain regions has a perimeter orthogonal to the length of the channel region. A first contact completely surrounds the perimeter of the source region. A second contact completely surrounds the perimeter of the drain region.

公开(公告)号：US20220310600A1

公开(公告)日：2022-09-29

申请号：US17842450

申请日：2022-06-16

Applicant: Intel Corporation

Inventor： Cory E. WEBER ,  Harold W. KENNEL ,  Willy RACHMADY ,  Gilbert DEWEY

IPC: H01L27/092 ,  H01L21/8258 ,  H01L27/12 ,  H01L21/02 ,  H01L29/78 ,  H01L29/06 ,  H01L21/8238

Abstract: Semiconductor nanowire devices having (111)-plane channel sidewalls and methods of fabricating semiconductor nanowire devices having (111)-plane channel sidewalls are described. For example, an integrated circuit structure includes a first semiconductor device including a plurality of vertically stacked nanowires disposed above a substrate, each of the nanowires comprising a discrete channel region having lateral sidewalls along a carrier transport direction. The integrated circuit structure also includes a second semiconductor device including a semiconductor fin disposed above the substrate, the semiconductor fin having a channel region with a top and side surfaces, the channel region having lateral sidewalls along a carrier transport direction.

公开(公告)号：US20190027503A1

公开(公告)日：2019-01-24

申请号：US15752241

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Aaron D. LILAK ,  Patrick MORROW ,  Stephen M. CEA ,  Rishabh MEHANDRU ,  Cory E. WEBER

IPC: H01L27/12 ,  H01L21/84 ,  H01L21/265 ,  H01L21/3115

Abstract: Embodiments of the present invention are directed to formation of fins with different active channel heights in a tri-gate or a Fin-FET device. In an embodiment, at least two fins are formed on a front side of the substrate. A gate structure extends over a top surface and a pair of sidewalls of at least a portion of the fins. In an embodiment, the substrate is thinned to expose the bottom surface of the fins. Next, backside etching may be performed on each fin to form active channel regions. The fins may be recessed to different depths, forming active channel regions with differing heights.

公开(公告)号：US20230046755A1

公开(公告)日：2023-02-16

申请号：US17978038

申请日：2022-10-31

Applicant: Intel Corporation

Inventor： Rishabh MEHANDRU ,  Patrick MORROW ,  Ranjith KUMAR ,  Cory E. WEBER ,  Seiyon KIM ,  Stephen M. CEA ,  Tahir GHANI

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/06 ,  H01L27/11 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/108 ,  H01L27/12

Abstract: Vertical integration schemes and circuit elements architectures for area scaling of semiconductor devices are described. In an example, an inverter structure includes a semiconductor fin separated vertically into an upper region and a lower region. A first plurality of gate structures is included for controlling the upper region of the semiconductor fin. A second plurality of gate structures is included for controlling the lower region of the semiconductor fin. The second plurality of gate structures has a conductivity type opposite the conductivity type of the first plurality of gate structures.

公开(公告)号：US20210043755A1

公开(公告)日：2021-02-11

申请号：US17080458

申请日：2020-10-26

Applicant: Intel Corporation

Inventor： Rishabh MEHANDRU ,  Patrick MORROW ,  Ranjith KUMAR ,  Cory E. WEBER ,  Seiyon KIM ,  Stephen M. CEA ,  Tahir GHANI

IPC: H01L29/66 ,  H01L29/78 ,  H01L27/12 ,  H01L21/84 ,  H01L27/108 ,  H01L21/8234 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/06 ,  H01L27/11 ,  H01L29/778

Abstract: Vertical integration schemes and circuit elements architectures for area scaling of semiconductor devices are described. In an example, an inverter structure includes a semiconductor fin separated vertically into an upper region and a lower region. A first plurality of gate structures is included for controlling the upper region of the semiconductor fin. A second plurality of gate structures is included for controlling the lower region of the semiconductor fin. The second plurality of gate structures has a conductivity type opposite the conductivity type of the first plurality of gate structures.

公开(公告)号：US20210036137A1

公开(公告)日：2021-02-04

申请号：US17072992

申请日：2020-10-16

Applicant: Intel Corporation

Inventor： Stephen M. CEA ,  Cory E. WEBER ,  Patrick H. KEYS ,  Seiyon KIM ,  Michael G. HAVERTY ,  Sadasivan SHANKAR

IPC: H01L29/775 ,  H01L29/66 ,  B82Y10/00 ,  H01L29/06 ,  H01L29/417 ,  H01L29/786 ,  H01L29/78

Abstract: Nanowire structures having wrap-around contacts are described. For example, a nanowire semiconductor device includes a nanowire disposed above a substrate. A channel region is disposed in the nanowire. The channel region has a length and a perimeter orthogonal to the length. A gate electrode stack surrounds the entire perimeter of the channel region. A pair of source and drain regions is disposed in the nanowire, on either side of the channel region. Each of the source and drain regions has a perimeter orthogonal to the length of the channel region. A first contact completely surrounds the perimeter of the source region. A second contact completely surrounds the perimeter of the drain region.