公开(公告)号：US20240220785A1

公开(公告)日：2024-07-04

申请号：US18408716

申请日：2024-01-10

Applicant: Intel Corporation

Inventor： Gautham Chinya ,  Huichu Liu ,  Arnab Raha ,  Debabrata Mohapatra ,  Cormac Brick ,  Lance Hacking

IPC: G06N3/063 ,  G06F9/38 ,  G06F9/448 ,  G06F9/50 ,  G06N5/04

CPC classification number: G06N3/063 ,  G06F9/3814 ,  G06F9/3877 ,  G06F9/4498 ,  G06F9/5027 ,  G06N5/04

Abstract: Methods and systems include a neural network system that includes a neural network accelerator comprising. The neural network accelerator includes multiple processing engines coupled together to perform arithmetic operations in support of an inference performed using the deep neural network system. The neural network accelerator also includes a schedule-aware tensor data distribution circuitry or software that is configured to load tensor data into the multiple processing engines in a load phase, extract output data from the multiple processing engines in an extraction phase, reorganize the extracted output data, and store the reorganized extracted output data to memory.

公开(公告)号：US11940907B2

公开(公告)日：2024-03-26

申请号：US17359217

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Martin-Thomas Grymel ,  David Bernard ,  Niall Hanrahan ,  Martin Power ,  Kevin Brady ,  Gary Baugh ,  Cormac Brick

IPC: G06F12/00 ,  G06F12/02 ,  G06N3/10

CPC classification number: G06F12/0207 ,  G06F12/0292 ,  G06N3/10

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed for sparse tensor storage for neural network accelerators. An example apparatus includes sparsity map generating circuitry to generate a sparsity map corresponding to a tensor, the sparsity map to indicate whether a data point of the tensor is zero, static storage controlling circuitry to divide the tensor into one or more storage elements, and a compressor to perform a first compression of the one or more storage elements to generate one or more compressed storage elements, the first compression to remove zero points of the one or more storage elements based on the sparsity map and perform a second compression of the one or more compressed storage elements, the second compression to store the one or more compressed storage elements contiguously in memory.

公开(公告)号：US11907827B2

公开(公告)日：2024-02-20

申请号：US16456707

申请日：2019-06-28

Applicant: Intel Corporation

Inventor： Gautham Chinya ,  Huichu Liu ,  Arnab Raha ,  Debabrata Mohapatra ,  Cormac Brick ,  Lance Hacking

IPC: G06N3/063 ,  G06N5/04 ,  G06F9/448 ,  G06F9/38 ,  G06F9/50

CPC classification number: G06N3/063 ,  G06F9/3814 ,  G06F9/3877 ,  G06F9/4498 ,  G06F9/5027 ,  G06N5/04

Abstract: Methods and systems include a neural network system that includes a neural network accelerator. The neural network accelerator includes multiple processing engines coupled together to perform arithmetic operations in support of an inference performed using the deep neural network system. The neural network accelerator also includes a schedule-aware tensor data distribution circuitry or software that is configured to load tensor data into the multiple processing engines in a load phase, extract output data from the multiple processing engines in an extraction phase, reorganize the extracted output data, and store the reorganized extracted output data to memory.

公开(公告)号：US11804851B2

公开(公告)日：2023-10-31

申请号：US16832804

申请日：2020-03-27

Applicant: Intel Corporation

Inventor： Gautham Chinya ,  Debabrata Mohapatra ,  Arnab Raha ,  Huichu Liu ,  Cormac Brick

IPC: H03M7/30 ,  G06F16/22 ,  G06N3/063 ,  G06N3/08 ,  G06N3/04

CPC classification number: H03M7/3082 ,  G06F16/2237 ,  G06N3/063 ,  G06N3/04 ,  G06N3/08

Abstract: Methods, systems, articles of manufacture, and apparatus are disclosed to decode zero-value-compression data vectors. An example apparatus includes: a buffer monitor to monitor a buffer for a header including a value indicative of compressed data; a data controller to, when the buffer includes compressed data, determine a first value of a sparse select signal based on (1) a select signal and (2) a first position in a sparsity bitmap, the first value of the sparse select signal corresponding to a processing element that is to process a portion of the compressed data; and a write controller to, when the buffer includes compressed data, determine a second value of a write enable signal based on (1) the select signal and (2) a second position in the sparsity bitmap, the second value of the write enable signal corresponding to the processing element that is to process the portion of the compressed data.

公开(公告)号：US11789646B2

公开(公告)日：2023-10-17

申请号：US17484780

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Niall Hanrahan ,  Martin Power ,  Kevin Brady ,  Martin-Thomas Grymel ,  David Bernard ,  Gary Baugh ,  Cormac Brick

IPC: G06F3/06 ,  G06F7/544

CPC classification number: G06F3/0656 ,  G06F3/0613 ,  G06F3/0625 ,  G06F3/0679 ,  G06F7/5443

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed that increase data reuse for multiply and accumulate (MAC) operations. An example apparatus includes a MAC circuit to process a first context of a set of a first type of contexts stored in a first buffer and a first context of a set of a second type of contexts stored in a second buffer. The example apparatus also includes control logic circuitry to, in response to determining that there is an additional context of the second type to be processed in the set of the second type of contexts, maintain the first context of the first type in the first buffer. The control logic circuitry is also to, in response to determining that there is an additional context of the first type to be processed in the set of the first type of contexts maintain the first context of the second type in the second buffer and iterate a pointer of the second buffer from a first position to a next position in the second buffer.

公开(公告)号：US20210397414A1

公开(公告)日：2021-12-23

申请号：US17358868

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Arnab Raha ,  Mark A. Anders ,  Martin Power ,  Martin Langhammer ,  Himanshu Kaul ,  Debabrata Mohapatra ,  Gautham Chinya ,  Cormac Brick ,  Ram Krishnamurthy

IPC: G06F7/544 ,  G06F7/527 ,  G06F5/01

Abstract: Systems, apparatuses and methods may provide for multi-precision multiply-accumulate (MAC) technology that includes a plurality of arithmetic blocks, wherein the plurality of arithmetic blocks each contain multiple multipliers, and wherein the logic is to combine multipliers one or more of within each arithmetic block or across multiple arithmetic blocks. In one example, one or more intermediate multipliers are of a size that is less than precisions supported by arithmetic blocks containing the one or more intermediate multipliers.

公开(公告)号：US20210326144A1

公开(公告)日：2021-10-21

申请号：US17359392

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Arnab Raha ,  Deepak Mathaikutty ,  Debabrata Mohapatra ,  Sang Kyun Kim ,  Gautham Chinya ,  Cormac Brick

IPC: G06F9/445 ,  G06F9/50 ,  G06F9/30 ,  G06N20/00 ,  H03K19/177 ,  H03K19/20

Abstract: Methods, apparatus, systems, and articles of manufacture to load data into an accelerator are disclosed. An example apparatus includes data provider circuitry to load a first section and an additional amount of compressed machine learning parameter data into a processor engine. Processor engine circuitry executes a machine learning operation using the first section of compressed machine learning parameter data. A compressed local data re-user circuitry determines if a second section is present in the additional amount of compressed machine learning parameter data. The processor engine circuitry executes a machine learning operation using the second section when the second section is present in the additional amount of compressed machine learning parameter data.

公开(公告)号：US20200228137A1

公开(公告)日：2020-07-16

申请号：US16832804

申请日：2020-03-27

Applicant: Intel Corporation

Inventor： Gautham Chinya ,  Debabrata Mohapatra ,  Arnab Raha ,  Huichu Liu ,  Cormac Brick

IPC: H03M7/30 ,  G06F16/22 ,  G06N3/063

Abstract: Methods, systems, articles of manufacture, and apparatus are disclosed to decode zero-value-compression data vectors. An example apparatus includes: a buffer monitor to monitor a buffer for a header including a value indicative of compressed data; a data controller to, when the buffer includes compressed data, determine a first value of a sparse select signal based on (1) a select signal and (2) a first position in a sparsity bitmap, the first value of the sparse select signal corresponding to a processing element that is to process a portion of the compressed data; and a write controller to, when the buffer includes compressed data, determine a second value of a write enable signal based on (1) the select signal and (2) a second position in the sparsity bitmap, the second value of the write enable signal corresponding to the processing element that is to process the portion of the compressed data.

公开(公告)号：US20200226453A1

公开(公告)日：2020-07-16

申请号：US16832601

申请日：2020-03-27

Applicant: Intel Corporation

Inventor： Eric Luk ,  Mohamed Elmalaki ,  Sara Almalih ,  Cormac Brick

IPC: G06N3/063 ,  G06N3/04 ,  G06N3/08

Abstract: Examples to determine a dynamic batch size of a layer are disclosed herein. An example apparatus to determine a dynamic batch size of a layer includes a layer operations controller to determine a layer ratio between a number of operations of a layer and weights of the layer, a comparator to compare the layer ratio to a number of operations per unit of memory size performed by a computation engine, and a batch size determination controller to, when the layer ratio is less than the number of operations per unit of memory size, determine the dynamic batch size of the layer.