公开(公告)号：US20220014363A1

公开(公告)日：2022-01-13

申请号：US17484820

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Andrea Basso ,  Santosh Ghosh ,  Manoj Sastry

IPC: H04L9/08 ,  H04L9/32 ,  H04L9/30 ,  G06F7/72

Abstract: Combined post-quantum security utilizing redefined polynomial calculation is described. An example of an apparatus includes a first circuit for key encapsulation operation; a second circuit for digital signature operation; and a NTT (Number Theoretic Transform) multiplier circuit, wherein the NTT multiplier circuit provides for polynomial multiplication for both the first circuit and the second circuit, wherein the apparatus is to remap coefficients of polynomials for the first circuit to a prime modulus for the second circuit, and perform polynomial multiplication for the first circuit utilizing the remapped coefficients of the polynomials for the first circuit.

公开(公告)号：US11218320B2

公开(公告)日：2022-01-04

申请号：US16455908

申请日：2019-06-28

Applicant: Intel Corporation

Inventor： Vikram Suresh ,  Sanu Mathew ,  Manoj Sastry ,  Santosh Ghosh ,  Raghavan Kumar ,  Rafael Misoczki

IPC: H04L29/06 ,  H04L9/32 ,  H04L9/08

Abstract: In one example an apparatus comprises a computer readable memory, hash logic to generate a message hash value based on an input message, signature logic to generate a signature to be transmitted in association with the message, the signature logic to apply a hash-based signature scheme to a private key to generate the signature comprising a public key, and accelerator logic to pre-compute at least one set of inputs to the signature logic. Other examples may be described.

公开(公告)号：US20210306155A1

公开(公告)日：2021-09-30

申请号：US16830844

申请日：2020-03-26

Applicant: Intel Corporation

Inventor： Manoj Sastry ,  Rafael Misoczki ,  Jordan Loney ,  David M. Wheeler

IPC: H04L9/32 ,  G06F21/72

Abstract: In one example an apparatus comprises a computer readable memory, a signing facility comprising a plurality of hardware security modules, and a state synchronization manager comprising processing circuitry to select, from the plurality of hardware security modules, a set of hardware security modules to be assigned to a digital signature process, the set of hardware security modules comprising at least a first hardware security module and a second hardware module, and assign a set of unique state synchronization counter sequences to the respective set of hardware security modules, the set of state synchronization counter sequences comprising at least a first state synchronization counter sequence and a second state synchronization counter sequence. Other examples may be described.

公开(公告)号：US20210026955A1

公开(公告)日：2021-01-28

申请号：US17031140

申请日：2020-09-24

Applicant: Intel Corporation

Inventor： Marcio Juliato ,  Manoj Sastry ,  Shabbir Ahmed ,  Christopher Gutierrez ,  Qian Wang ,  Vuk Lesi

IPC: G06F21/55 ,  G06F21/71 ,  G06F21/85

Abstract: A platform comprising numerous reconfigurable circuit components arranged to operate as primary and redundant circuits is provided. The platform further comprises security circuitry arranged to monitor the primary circuit for anomalies and reconfigurable circuit arranged to disconnect the primary circuit from a bus responsive to detection of an anomaly. Furthermore, the present disclosure provides for the quarantine, refurbishment and designation as redundant, the anomalous circuit.

公开(公告)号：US20190319796A1

公开(公告)日：2019-10-17

申请号：US16456034

申请日：2019-06-28

Applicant: Intel Corporation

Inventor： SANTOSH GHOSH ,  Vikram Suresh ,  Sanu Mathew ,  Manoj Sastry ,  Andrew H. Reinders ,  Raghavan Kumar ,  Rafael Misoczki

IPC: H04L9/32 ,  H04L9/08 ,  H04L9/30 ,  H04L9/06

Abstract: In one example an apparatus comprises a computer readable memory, an XMSS verification manager logic to manage XMSS verification functions, a one-time signature and public key generator logic, a chain function logic to implement chain function algorithms, a low latency SHA3 hardware engine, and a register bank communicatively coupled to the XMSS verification manager logic. Other examples may be described.

公开(公告)号：US12301599B2

公开(公告)日：2025-05-13

申请号：US17484197

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Marcio Juliato ,  Javier Perez-Ramirez ,  Vuk Lesi ,  Dave Cavalcanti ,  Manoj Sastry ,  Christopher Gutierrez ,  Qian Wang ,  Shabbir Ahmed

IPC: H04L9/40

Abstract: Systems, apparatuses and methods may provide for technology that detects one or more non-compliant nodes with respect to a timing schedule, detects one or more compliant nodes with respect to the timing schedule, and identifies a malicious node based on positions of the one or more non-compliant nodes and the one or more compliant nodes in a network topography. The non-compliant node(s) and the compliant node(s) may be detected based on post-synchronization messages, historical attribute data and/or plane diversity data.

公开(公告)号：US12205065B2

公开(公告)日：2025-01-21

申请号：US16994089

申请日：2020-08-14

Applicant: Intel Corporation

Inventor： Christopher Gutierrez ,  Marcio Juliato ,  Qian Wang ,  Shabbir Ahmed ,  Vuk Lesi ,  Manoj Sastry

IPC: G06Q10/0833 ,  G08G1/00 ,  H04L9/08 ,  H04L9/32

Abstract: Systems, apparatuses, and methods to attest to and verify the integrity of cargo during transport by an autonomous vehicle are provided. An autonomous vehicle can discretize parameters associated with transportation of cargo and can generate a keyed hash digest from the discretized parameters. The keyed hash digest can be sent to a stakeholder in the transportation of the cargo to attest to the integrity of the cargo during transport.

公开(公告)号：US20250005209A1

公开(公告)日：2025-01-02

申请号：US18343609

申请日：2023-06-28

Applicant: Intel Corporation

Inventor： Debayan Das ,  Santosh Ghosh ,  Manoj Sastry

IPC: G06F21/75

Abstract: Techniques for attenuation and obfuscation to mitigate power and/or electromagnetic (EM) field attacks on encryption circuitry are described. In certain examples, a system includes a processor core; and an accelerator coupled to the processor core, the accelerator comprising: encryption circuitry, coupled to a power source, to encrypt data into encrypted data, time-domain obfuscation control circuitry to connect and disconnect one or more capacitors to the encryption circuitry during the encrypt to provide obfuscation across a time-domain to maintain a software observable power consumption of the accelerator to about a value, and signature attenuation control circuitry to selectively connect the encryption circuitry during the encrypt to a shunt to drain power to maintain the software observable power consumption of the accelerator at about the value.

公开(公告)号：US12137169B2

公开(公告)日：2024-11-05

申请号：US17854911

申请日：2022-06-30

Applicant: Intel Corporation

Inventor： Santosh Ghosh ,  Vikram Suresh ,  Sanu Mathew ,  Manoj Sastry ,  Andrew H. Reinders ,  Raghavan Kumar ,  Rafael Misoczki

IPC: H04L9/32 ,  H04L9/00 ,  H04L9/06 ,  H04L9/08 ,  H04L9/30

Abstract: In one example an apparatus comprises a computer readable memory, an XMSS verification manager logic to manage XMSS verification functions, a one-time signature and public key generator logic, a chain function logic to implement chain function algorithms, a low latency SHA3 hardware engine, and a register bank communicatively coupled to the XMSS verification manager logic. Other examples may be described.

公开(公告)号：US12095782B2

公开(公告)日：2024-09-17

申请号：US17706955

申请日：2022-03-29

Applicant: Intel Corporation

Inventor： Christopher Gutierrez ,  Vuk Lesi ,  Manoj Sastry ,  Christopher Hall ,  Marcio Juliato ,  Shabbir Ahmed ,  Qian Wang

IPC: H04L9/40 ,  H04J3/06

CPC classification number: H04L63/1416 ,  H04J3/0667 ,  H04L63/145 ,  H04L63/1475

Abstract: Techniques to secure a time sensitive network are described. An apparatus may establish a data stream between a first device and a second device in a network domain, the network domain includes a plurality of switching nodes, receive messages from the first device by the second device in the network domain, the messages to comprise time information to synchronize a first clock for the first device and a second clock for the second device to a network time for the network domain, update a correction field for a received message with a residence time and time delay value by the second device, determine whether the updated message is benign or malicious, update the correction field for the updated message with an inference time when the updated message is benign, and prevent relay of the updated message to other devices in the network domain when the updated message is malicious.