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    Hardware for miss handling from a translation protection data structure
    21.
    发明授权
    Hardware for miss handling from a translation protection data structure 有权

    公开(公告)号：US10089244B1

    公开(公告)日：2018-10-02

    申请号：US15475646

    申请日：2017-03-31

    Applicant: INTEL CORPORATION

    Inventor： Paul Caprioli ,  Jeffrey J. Cook

    IPC: G06F12/00 ,  G06F12/128 ,  G06F12/1045 ,  G06F12/122 ,  G06F12/0831 ,  G06F12/1009

    Abstract: A processor includes a memory to store original code and a fingerprint data structure, which stores, in a way thereof, an entry including a physical address for a page and a stored fingerprint generated from the page of the original code. A core includes a translation protection data structure (TPDS) to detect modification to the page, wherein the core is to, upon execution of a translation check instruction included within a translated page code corresponding to the page, transmit, to the TPDS, a modification check request having the physical address of the page in the memory and the way of the fingerprint data structure. A hardware TPDS miss handler is coupled to the core and is to process a miss request received from the TPDS responsive to the physical address not being present in the TPDS.

    TECHNOLOGIES FOR TRANSLATION CACHE MANAGEMENT IN BINARY TRANSLATION SYSTEMS
    23.
    发明申请
    TECHNOLOGIES FOR TRANSLATION CACHE MANAGEMENT IN BINARY TRANSLATION SYSTEMS 审中-公开

    公开(公告)号：US20180088921A1

    公开(公告)日：2018-03-29

    申请号：US15274624

    申请日：2016-09-23

    Applicant: Intel Corporation

    Inventor： Paul Caprioli ,  Jeffrey J. Cook

    IPC: G06F9/45

    CPC classification number: G06F8/52 ,  G06F9/30

    Abstract: Technologies for optimized binary translation include a computing device that determines a cost-benefit metric associated with each translated code block of a translation cache. The cost-benefit metric is indicative of translation cost and performance benefit associated with the translated code block. The translation cost may be determined by measuring translation time of the translated code block. The cost-benefit metric may be calculated using a weighted cost-benefit function based on an expected workload of the computing device. In response to determining to free space in the translation cache, the computing device determines whether to discard each translated code block as a function of the cost-benefit metric. In response to determining to free space in the translation cache, the computing device may increment an iteration count and skip each translated code block if the iteration count modulo the corresponding cost-benefit metric is non-zero. Other embodiments are described and claimed.

    Return-target restrictive return from procedure instructions, processors, methods, and systems
    24.
    发明授权
    Return-target restrictive return from procedure instructions, processors, methods, and systems 有权

    公开(公告)号：US09703948B2

    公开(公告)日：2017-07-11

    申请号：US14229822

    申请日：2014-03-28

    Applicant: Intel Corporation

    Inventor： Paul Caprioli

    IPC: G06F9/44 ,  G06F9/45 ,  G06F21/54 ,  G06F9/30

    CPC classification number: G06F21/54 ,  G06F9/3005 ,  G06F9/30054 ,  G06F9/30145 ,  G06F2221/034

    Abstract: A processor includes a decode unit to decode a return target restrictive return from procedure (RTR return) instruction. A return target restriction unit is responsive to the RTR return instruction to determine whether to restrict an attempt by the RTR return instruction to make a control flow transfer to an instruction at a return address corresponding to the RTR return instruction. The determination is based on compatibility of a type of the instruction at the return address with the RTR return instruction and based on compatibility of first return target restrictive information (RTR information) of the RTR return instruction with second RTR information of the instruction at the return address. A control flow transfer unit is responsive to the RTR return instruction to transfer control flow to the instruction at the return address when the return target restriction unit determines not to restrict the attempt.

    Implementation Of Processor Trace In A Processor That Supports Binary Translation
    25.
    发明申请
    Implementation Of Processor Trace In A Processor That Supports Binary Translation 有权
    在支持二进制翻译的处理器中实现处理器跟踪

    公开(公告)号：US20160357658A1

    公开(公告)日：2016-12-08

    申请号：US14732028

    申请日：2015-06-05

    Applicant: Intel Corporation

    Inventor： Furat F. Afram ,  Jeffrey J. Cook ,  Paul Caprioli

    IPC: G06F11/36

    CPC classification number: G06F11/3624 ,  G06F11/3636

    Abstract: In an embodiment, a processor includes execution logic to execute binary translated (BT) code that is translated from native architecture (NA) code. The processor also includes processor trace (PT) logic to output trace information responsive to execution of a BT direct branch instruction in the BT code when the NA code includes an NA direct branch instruction that corresponds to the BT direct branch instruction. The trace information is to include an indication of an NA outcome associated with an execution of the NA direct branch instruction. The trace information is to be based on a BT outcome associated with the execution of the BT direct branch instruction. Other embodiments are described and claimed.

    Abstract translation: 在一个实施例中，处理器包括执行逻辑以执行从本地架构（NA）代码转换的二进制翻译（BT）代码。 当NA码包括对应于BT直接分支指令的NA直接分支指令时，处理器还包括响应于BT代码中的BT直接分支指令的执行而输出跟踪信息的处理器跟踪（PT）逻辑。 跟踪信息包括与NA直接分支指令的执行相关联的NA结果的指示。 跟踪信息是基于与BT直接分支指令的执行相关联的BT结果。 描述和要求保护其他实施例。

    Apparatuses, methods, and systems for swizzle operations in a configurable spatial accelerator
    28.
    发明授权
    Apparatuses, methods, and systems for swizzle operations in a configurable spatial accelerator 有权

    公开(公告)号：US10817291B2

    公开(公告)日：2020-10-27

    申请号：US16370915

    申请日：2019-03-30

    Applicant: Intel Corporation

    Inventor： Jesus Corbal ,  Rohan Sharma ,  Simon Steely, Jr. ,  Chinmay Ashok ,  Kent D. Glossop ,  Dennis Bradford ,  Paul Caprioli ,  Louise Huot ,  Kermin ChoFleming ,  Barry Tannenbaum

    IPC: G06F9/30 ,  G06F15/82

    Abstract: Systems, methods, and apparatuses relating to swizzle operations and disable operations in a configurable spatial accelerator (CSA) are described. Certain embodiments herein provide for an encoding system for a specific set of swizzle primitives across a plurality of packed data elements in a CSA. In one embodiment, a CSA includes a plurality of processing elements, a circuit switched interconnect network between the plurality of processing elements, and a configuration register within each processing element to store a configuration value having a first portion that, when set to a first value that indicates a first mode, causes the processing element to pass an input value to operation circuitry of the processing element without modifying the input value, and, when set to a second value that indicates a second mode, causes the processing element to perform a swizzle operation on the input value to form a swizzled input value before sending the swizzled input value to the operation circuitry of the processing element, and a second portion that causes the processing element to perform an operation indicated by the second portion the configuration value on the input value in the first mode and the swizzled input value in the second mode with the operation circuitry.

    Control transfer override
    29.
    发明授权
    Control transfer override 有权

    公开(公告)号：US10241787B2

    公开(公告)日：2019-03-26

    申请号：US14231509

    申请日：2014-03-31

    Applicant: Intel Corporation

    Inventor： Paul Caprioli

    IPC: G06F9/00 ,  G06F11/00 ,  G06F21/00 ,  G06F21/52 ,  G06F21/72

    Abstract: Embodiments of an invention for control transfer overrides are disclosed. In one embodiment, a processor includes an instruction unit to receive a control transfer instruction. The instruction unit includes a transfer override register to provide an alternative target for the control transfer instruction.

    Accelerated interlane vector reduction instructions
    30.
    发明授权
    Accelerated interlane vector reduction instructions 有权

    公开(公告)号：US10209989B2

    公开(公告)日：2019-02-19

    申请号：US15452479

    申请日：2017-03-07

    Applicant: Intel Corporation

    Inventor： Paul Caprioli ,  Abhay S. Kanhere ,  Jeffrey J. Cook ,  Muawya M. Al-Otoom

    IPC: G06F7/38 ,  G06F9/00 ,  G06F9/44 ,  G06F9/30 ,  G06F9/38

    Abstract: A vector reduction instruction is executed by a processor to provide efficient reduction operations on an array of data elements. The processor includes vector registers. Each vector register is divided into a plurality of lanes, and each lane stores the same number of data elements. The processor also includes execution circuitry that receives the vector reduction instruction to reduce the array of data elements stored in a source operand into a result in a destination operand using a reduction operator. Each of the source operand and the destination operand is one of the vector registers. Responsive to the vector reduction instruction, the execution circuitry applies the reduction operator to two of the data elements in each lane, and shifts one or more remaining data elements when there is at least one of the data elements remaining in each lane.

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