中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

43 records (took 0.018 seconds)

    PROGRAMMABLE NEURON CORE WITH ON-CHIP LEARNING AND STOCHASTIC TIME STEP CONTROL
    22.
    发明申请
    PROGRAMMABLE NEURON CORE WITH ON-CHIP LEARNING AND STOCHASTIC TIME STEP CONTROL 审中-公开

    公开(公告)号：US20180089557A1

    公开(公告)日：2018-03-29

    申请号：US15276111

    申请日：2016-09-26

    Applicant: INTEL CORPORATION

    Inventor： Raghavan Kumar ,  Gregory K. Chen ,  Huseyin Ekin Sumbul ,  Phil Knag

    IPC: G06N3/063 ,  G06N3/08 ,  G06N3/04

    CPC classification number: G06N3/049 ,  G06N3/063 ,  G06N3/088

    Abstract: An integrated circuit (IC), as a computation block of a neuromorphic system, includes a time step controller to activate a time step update signal for performing a time-multiplexed selection of a group of neuromorphic states to update. The IC includes a first circuitry to, responsive to detecting the time step update signal for a selected group of neuromorphic states: generate an outgoing data signal in response to determining that a first membrane potential of the selected group of neuromorphic states exceeds a threshold value, wherein the outgoing data signal includes an identifier that identifies the selected group of neuromorphic states and a memory address (wherein the memory address corresponds to a location in a memory block associated with the integrated circuit), and update a state of the selected group of neuromorphic states in response to generation of the outgoing data signal.

    Programmable interface to in-memory cache processor
    27.
    发明授权
    Programmable interface to in-memory cache processor 有权

    公开(公告)号：US11151046B2

    公开(公告)日：2021-10-19

    申请号：US16921685

    申请日：2020-07-06

    Applicant: Intel Corporation

    Inventor： Amrita Mathuriya ,  Sasikanth Manipatruni ,  Victor Lee ,  Huseyin Sumbul ,  Gregory Chen ,  Raghavan Kumar ,  Phil Knag ,  Ram Krishnamurthy ,  Ian Young ,  Abhishek Sharma

    IPC: G06F12/0875 ,  G06N3/063 ,  G06N3/04 ,  G06F3/06 ,  G06F8/41 ,  G06F9/455

    Abstract: The present disclosure is directed to systems and methods of implementing a neural network using in-memory mathematical operations performed by pipelined SRAM architecture (PISA) circuitry disposed in on-chip processor memory circuitry. A high-level compiler may be provided to compile data representative of a multi-layer neural network model and one or more neural network data inputs from a first high-level programming language to an intermediate domain-specific language (DSL). A low-level compiler may be provided to compile the representative data from the intermediate DSL to multiple instruction sets in accordance with an instruction set architecture (ISA), such that each of the multiple instruction sets corresponds to a single respective layer of the multi-layer neural network model. Each of the multiple instruction sets may be assigned to a respective SRAM array of the PISA circuitry for in-memory execution. Thus, the systems and methods described herein beneficially leverage the on-chip processor memory circuitry to perform a relatively large number of in-memory vector/tensor calculations in furtherance of neural network processing without burdening the processor circuitry.

    PROGRAMMABLE INTERFACE TO IN-MEMORY CACHE PROCESSOR
    29.
    发明申请
    PROGRAMMABLE INTERFACE TO IN-MEMORY CACHE PROCESSOR 审中-公开

    公开(公告)号：US20200334161A1

    公开(公告)日：2020-10-22

    申请号：US16921685

    申请日：2020-07-06

    Applicant: Intel Corporation

    Inventor： Amrita Mathuriya ,  Sasikanth Manipatruni ,  Victor Lee ,  Huseyin Sumbul ,  Gregory Chen ,  Raghavan Kumar ,  Phil Knag ,  Ram Krishnamurthy ,  IAN YOUNG ,  Abhishek Sharma

    IPC: G06F12/0875 ,  G06N3/063 ,  G06N3/04 ,  G06F3/06 ,  G06F8/41 ,  G06F9/455

    Abstract: The present disclosure is directed to systems and methods of implementing a neural network using in-memory mathematical operations performed by pipelined SRAM architecture (PISA) circuitry disposed in on-chip processor memory circuitry. A high-level compiler may be provided to compile data representative of a multi-layer neural network model and one or more neural network data inputs from a first high-level programming language to an intermediate domain-specific language (DSL). A low-level compiler may be provided to compile the representative data from the intermediate DSL to multiple instruction sets in accordance with an instruction set architecture (ISA), such that each of the multiple instruction sets corresponds to a single respective layer of the multi-layer neural network model. Each of the multiple instruction sets may be assigned to a respective SRAM array of the PISA circuitry for in-memory execution. Thus, the systems and methods described herein beneficially leverage the on-chip processor memory circuitry to perform a relatively large number of in-memory vector/tensor calculations in furtherance of neural network processing without burdening the processor circuitry.

Patent Agency Ranking