公开(公告)号：US09317421B2

公开(公告)日：2016-04-19

申请号：US14039129

申请日：2013-09-27

Applicant: Intel Corporation

Inventor： Robert J. Royer, Jr.

IPC: G06F12/00 ,  G06F12/02 ,  G06F3/06

CPC classification number: G06F3/0604 ,  G06F3/06 ,  G06F3/064 ,  G06F3/0659 ,  G06F3/0665 ,  G06F3/0679 ,  G06F12/0238 ,  G06F2212/202 ,  G06F2212/7201 ,  G06F2212/7204

Abstract: Apparatus, systems, and methods to manage memory operations are described. In one embodiment, an electronic device comprises a processor and a memory control logic to retrieve a global sequence number from a memory device, receive a read request for data stored in a logical block address in the memory device, retrieve a media sequence number from the logical block address in the memory device, and return a null response in lieu of the data stored in the logical block address when the media sequence number is older than the global sequence number. Other embodiments are also disclosed and claimed.

Abstract translation: 描述了管理存储器操作的装置，系统和方法。 在一个实施例中，电子设备包括处理器和存储器控制逻辑以从存储器设备检索全局序列号，接收对存储在存储器设备中的逻辑块地址中的数据的读取请求，从存储器设备中检索媒体序列号 逻辑块地址，并且当媒体序列号比全局序列号更早时，返回空响应代替存储在逻辑块地址中的数据。 还公开并要求保护其他实施例。

公开(公告)号：US09053014B2

公开(公告)日：2015-06-09

申请号：US14024724

申请日：2013-09-12

Applicant: Intel corporation

Inventor： Amber D. Huffman ,  Suryaprasad Kareenahalli ,  Robert J. Royer, Jr. ,  Chai Huat Gan

IPC: G06F12/00 ,  G06F12/02 ,  G11C16/10 ,  G11C16/32

CPC classification number: G06F12/0246 ,  G11C16/10 ,  G11C16/32

Abstract: A system and method of controlling a flash memory device such as a NAND memory device may involve receiving a command to execute an operation. A Ready/Busy contact of the memory device may be pulsed low in response to determining that execution of the operation has completed.

Abstract translation: 控制诸如NAND存储设备的闪存设备的系统和方法可以包括接收执行操作的命令。 响应于确定操作的执行已经完成，存储器件的就绪/忙触点可以被脉冲为低脉冲。