公开(公告)号：US20190042049A1

公开(公告)日：2019-02-07

申请号：US16024654

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Arvind Kumar ,  Antonio Cheng ,  Chai Huat Gan

IPC: G06F3/041 ,  G06F13/42

CPC classification number: G06F3/0416 ,  G06F13/4278 ,  G06F2203/04101 ,  G06F2203/04104

Abstract: Technology for an electronic circuit is described. The electronic circuit can include one or more timed general-purpose input/output (GPIO) pins and a controller. The controller can receive touch sensor data pulses from a plurality of touch sensor integrated circuits (ICs) that are each communicatively coupled to the electronic circuit. A first touch sensor data pulse received from a first touch sensor IC in the plurality of touch sensor ICs can be time synchronized with a second touch sensor data pulse received from a second touch sensor IC in the plurality of touch sensor ICs using the one or more timed GPIO pins. The controller can combine the touch sensor data pulses received time synchronously from each of the plurality of touch sensor ICs to produce joint touch sensor data. The controller can perform joint processing of the joint touch sensor data.

公开(公告)号：US11036409B2

公开(公告)日：2021-06-15

申请号：US15843545

申请日：2017-12-15

Applicant: Intel Corporation

Inventor： Zhenyu Zhu ,  Chai Huat Gan ,  Mikal Hunsaker

IPC: G06F3/06 ,  G06F12/02 ,  G06F13/42 ,  G06F13/16

Abstract: A first signal may be received from a memory device at a first interconnect terminal of a number of interconnect terminals via a serial communication interface that indicates the memory device includes a NAND type memory device. Whether a second signal that indicates the NAND type memory device is initialized has been received from the memory device at a second interconnect terminal of the number of interconnect terminals may be determined. An operation associated with the NAND type memory device may be performed at the second interconnect terminal and a third interconnect terminal in response to determining the second signal has been received from the memory device indicating the NAND type memory device is initialized.

公开(公告)号：US20190155753A1

公开(公告)日：2019-05-23

申请号：US16258828

申请日：2019-01-28

Applicant: Intel Corporation

Inventor： Zhenyu Zhu ,  Mikal Hunsaker ,  Chai Huat Gan

IPC: G06F12/14 ,  G06F21/64 ,  G06F21/79 ,  G06F21/60

Abstract: In one embodiment, an apparatus includes: an interface controller to receive a request from an external device coupled to the apparatus to access a flash memory coupled to the apparatus, the request comprising an access request to a replay protection monotonic counter (RPMC) of the flash memory; and a flash controller coupled to the interface controller. In turn, the flash controller includes: an atomic sequencer to arbitrate accesses to the RPMC by a plurality of components; and a mapper to map the access request to a selected counter of the RPMC associated with the external device. Other embodiments are described and claimed.

公开(公告)号：US10860500B2

公开(公告)日：2020-12-08

申请号：US16258828

申请日：2019-01-28

Applicant: Intel Corporation

Inventor： Zhenyu Zhu ,  Mikal Hunsaker ,  Chai Huat Gan

IPC: G06F12/00 ,  G06F12/14 ,  G06F21/60 ,  G06F21/79 ,  G06F21/64 ,  G06F21/10

Abstract: In one embodiment, an apparatus includes: an interface controller to receive a request from an external device coupled to the apparatus to access a flash memory coupled to the apparatus, the request comprising an access request to a replay protection monotonic counter (RPMC) of the flash memory; and a flash controller coupled to the interface controller. In turn, the flash controller includes: an atomic sequencer to arbitrate accesses to the RPMC by a plurality of components; and a mapper to map the access request to a selected counter of the RPMC associated with the external device. Other embodiments are described and claimed.

公开(公告)号：US10761641B2

公开(公告)日：2020-09-01

申请号：US16024654

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Arvind Kumar ,  Antonio Cheng ,  Chai Huat Gan

IPC: G06F3/041 ,  G06F13/42

Abstract: Technology for an electronic circuit is described. The electronic circuit can include one or more timed general-purpose input/output (GPIO) pins and a controller. The controller can receive touch sensor data pulses from a plurality of touch sensor integrated circuits (ICs) that are each communicatively coupled to the electronic circuit. A first touch sensor data pulse received from a first touch sensor IC in the plurality of touch sensor ICs can be time synchronized with a second touch sensor data pulse received from a second touch sensor IC in the plurality of touch sensor ICs using the one or more timed GPIO pins. The controller can combine the touch sensor data pulses received time synchronously from each of the plurality of touch sensor ICs to produce joint touch sensor data. The controller can perform joint processing of the joint touch sensor data.

公开(公告)号：US09053014B2

公开(公告)日：2015-06-09

申请号：US14024724

申请日：2013-09-12

Applicant: Intel corporation

Inventor： Amber D. Huffman ,  Suryaprasad Kareenahalli ,  Robert J. Royer, Jr. ,  Chai Huat Gan

IPC: G06F12/00 ,  G06F12/02 ,  G11C16/10 ,  G11C16/32

CPC classification number: G06F12/0246 ,  G11C16/10 ,  G11C16/32

Abstract: A system and method of controlling a flash memory device such as a NAND memory device may involve receiving a command to execute an operation. A Ready/Busy contact of the memory device may be pulsed low in response to determining that execution of the operation has completed.

Abstract translation: 控制诸如NAND存储设备的闪存设备的系统和方法可以包括接收执行操作的命令。 响应于确定操作的执行已经完成，存储器件的就绪/忙触点可以被脉冲为低脉冲。