公开(公告)号：US20210194468A1

公开(公告)日：2021-06-24

申请号：US16725689

申请日：2019-12-23

Applicant: Intel Corporation

Inventor： Amit Agarwal ,  Steven Hsu ,  Anupama Ambardar Thaploo ,  Simeon Realov ,  Ram Krishnamurthy

IPC: H03K3/037 ,  H03K3/038 ,  G01R31/3177 ,  G01R31/317

Abstract: A family of novel, low power, min-drive strength, double-edge triggered (DET) input data multiplexer (Mux-D) scan flip-flop (FF) is provided. The flip-flop takes the advantage of no state node in the slave to remove data inverters in a traditional DET FF to save power, without affecting the flip-flop functionality under coupling/glitch scenarios.

公开(公告)号：US10862462B2

公开(公告)日：2020-12-08

申请号：US16670830

申请日：2019-10-31

Applicant: Intel Corporation

Inventor： Steven K. Hsu ,  Amit Agarwal ,  Simeon Realov

IPC: H03K3/037 ,  H03K19/00

Abstract: An apparatus is provided which comprises: a first flip-flop (FF) cell with a data path multiplexed with a scan-data path, wherein the scan-data path is independent of a min-delay buffer, wherein the first FF cell has a memory element formed of at least two inverting cells, wherein the two inverting cells are coupled together via a common node; and a second FF cell with a data path multiplexed with a scan-data path, wherein the scan-data path of the second FF cell is independent of a min-delay buffer, and wherein the scan-data path of the second FF cell is coupled to the common node of the first FF cell.

公开(公告)号：US20200150179A1

公开(公告)日：2020-05-14

申请号：US16681691

申请日：2019-11-12

Applicant: Intel Corporation

Inventor： Amit Agarwal ,  Ram Krishnamurthy ,  Satish Damaraju ,  Steven Hsu ,  Simeon Realov

IPC: G01R31/317 ,  G01R31/3185 ,  H03K3/037 ,  G01R31/3177

Abstract: An apparatus is provided which comprises: a multi-bit quad latch with an internally coupled level sensitive scan circuitry; and a combinational logic coupled to an output of the multi-bit quad latch. Another apparatus is provided which comprises: a plurality of sequential logic circuitries; and a clocking circuitry comprising inverters, wherein the clocking circuitry is shared by the plurality of sequential logic circuitries.

公开(公告)号：US10473718B2

公开(公告)日：2019-11-12

申请号：US15846047

申请日：2017-12-18

Applicant: Intel Corporation

Inventor： Amit Agarwal ,  Ram Krishnamurthy ,  Satish Damaraju ,  Steven Hsu ,  Simeon Realov

IPC: G01R31/317 ,  G01R31/3177 ,  H03K3/037 ,  G01R31/3185

Abstract: An apparatus is provided which comprises: a multi-bit quad latch with an internally coupled level sensitive scan circuitry; and a combinational logic coupled to an output of the multi-bit quad latch. Another apparatus is provided which comprises: a plurality of sequential logic circuitries; and a clocking circuitry comprising inverters, wherein the clocking circuitry is shared by the plurality of sequential logic circuitries.

公开(公告)号：US20180062658A1

公开(公告)日：2018-03-01

申请号：US15244839

申请日：2016-08-23

Applicant: Intel Corporation

Inventor： Steven K. Hsu ,  Amit Agarwal ,  Iqbal R. Rajwani ,  Simeon Realov ,  Ram K. Krishnamurthy

IPC: H03K19/0944 ,  H03K19/20 ,  H03K19/00

CPC classification number: H03K19/0944 ,  H03K19/0013 ,  H03K19/20

Abstract: An apparatus is provided which comprises: a clock node; a test node; an enable node; and an AND-OR-INVERT (AOI) static latch coupled to the clock node, test node, and enable node, wherein the AOI static latch has embedded NOR functionality. Another apparatus comprises: a critical timing path having a pass-gate based integrated clock gate; and a non-critical timing path electrically coupled to the critical timing path, wherein the non-critical timing path includes an AND-OR-Inverter (AOI) based integrated clock gate with embedded NOR functionality.

公开(公告)号：US20180062625A1

公开(公告)日：2018-03-01

申请号：US15246445

申请日：2016-08-24

Applicant: Intel Corporation

Inventor： Amit Agarwal ,  Steven K. Hsu ,  Simeon Realov ,  Ram K. Krishnamurthy

IPC: H03K3/3562 ,  H03K19/00 ,  H03K19/20

CPC classification number: H03K3/3562 ,  H03K3/0375 ,  H03K19/0002 ,  H03K19/20

Abstract: An apparatus is provided which comprises: a multiplexer which is gated by a clock; and a flip-flop coupled to the multiplexer, wherein the flip-flop has a chain of at least four inverters one of which has an input to receive the clock.