公开(公告)号：US20180145663A1

公开(公告)日：2018-05-24

申请号：US15860562

申请日：2018-01-02

Applicant: INTEL CORPORATION

Inventor： Amit Agarwal ,  Steven K. Hsu ,  Simeon Realov ,  Iqbal R. Rajwani ,  Ram K. Krishnamurthy

IPC: H03K3/3562 ,  H03K3/037

CPC classification number: H03K3/3562 ,  H03K3/0372 ,  H03K3/35625

Abstract: An apparatus is provided which comprises: a clock node; a first inverter having an input coupled to the clock node; a data node; a master latch with a shared p-type keeper coupled to an output of the first inverter, the master latch coupled to the data node; and a slave latch coupled to an output of the master latch, the slave latch having a shared p-type keeper and a shared n-type footer, wherein the shared p-type keeper and the shared n-type footer of the slave latch are coupled to the clock node and the input of the first inverter.

公开(公告)号：US20180091150A1

公开(公告)日：2018-03-29

申请号：US15277189

申请日：2016-09-27

Applicant: Intel Corporation

Inventor： Steven K. Hsu ,  Amit Agarwal ,  Ram K. Krishnamurthy

IPC: H03K19/0185 ,  H03K3/037

CPC classification number: H03K19/018521 ,  H03K3/037 ,  H03K3/0372

Abstract: Some embodiments include apparatus and methods using an input stage and an output stage of a circuit. The input stage operates to receive an input signal and a clock signal and to provide an internal signal at an internal node based at least in part on the input signal. The input signal has levels in a first voltage range. The internal signal has levels in a second voltage range greater than the first voltage range. The output stage operates to receive the internal signal, the clock signal, and an additional signal generated based on the input signal. The output stage provides an output signal based at least in part on the input signal and the additional signal. The output signal has a third voltage range greater than the first voltage range.

公开(公告)号：US20180069538A1

公开(公告)日：2018-03-08

申请号：US15260180

申请日：2016-09-08

Applicant: Intel Corporation

Inventor： Amit Agarwal ,  Steven K. Hsu ,  Ram K. Krishnamurthy

IPC: H03K3/356 ,  H03K3/012

CPC classification number: H03K3/012 ,  H03K3/35625

Abstract: An apparatus is provided which comprises a clock inverter having an input coupled to a clock node, the clock inverter having an output, wherein the clock inverter has an N-well which is coupled to a first power supply; and a plurality of sequential logics coupled to the output of the clock inverter and also coupled to the clock node, wherein at least one sequential logics of the plurality of the sequential logics has an N-well which is coupled to a second power supply, wherein the second power supply has a voltage level lower than a voltage level of the first power supply.