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    Shared keeper and footer flip-flop
    3.
    发明授权
    Shared keeper and footer flip-flop 有权

    公开(公告)号：US10193536B2

    公开(公告)日：2019-01-29

    申请号：US15860562

    申请日：2018-01-02

    Applicant: INTEL CORPORATION

    Inventor： Amit Agarwal ,  Steven K. Hsu ,  Simeon Realov ,  Iqbal R. Rajwani ,  Ram K. Krishnamurthy

    IPC: H03K3/3562 ,  H03K3/037

    Abstract: An apparatus is provided which comprises: a clock node; a first inverter having an input coupled to the clock node; a data node; a master latch with a shared p-type keeper coupled to an output of the first inverter, the master latch coupled to the data node; and a slave latch coupled to an output of the master latch, the slave latch having a shared p-type keeper and a shared n-type footer, wherein the shared p-type keeper and the shared n-type footer of the slave latch are coupled to the clock node and the input of the first inverter.

    High performance fast Mux-D scan flip-flop
    4.
    发明授权
    High performance fast Mux-D scan flip-flop 有权

    公开(公告)号：US11296681B2

    公开(公告)日：2022-04-05

    申请号：US16726020

    申请日：2019-12-23

    Applicant: Intel Corporation

    Inventor： Amit Agarwal ,  Steven Hsu ,  Simeon Realov ,  Mahesh Kumashikar ,  Ram Krishnamurthy

    IPC: H03K3/00 ,  H03K3/037 ,  G01R31/3177 ,  H03K3/038 ,  H03K19/20

    Abstract: A fast Mux-D scan flip-flop is provided, which bypasses a scan multiplexer to a master keeper side path, removing delay overhead of a traditional Mux-D scan topology. The design is compatible with simple scan methodology of Mux-D scan, while preserving smaller area and small number of inputs/outputs. Since scan Mux is not in the forward critical path, circuit topology has similar high performance as level-sensitive scan flip-flop and can be easily converted into bare pass-gate version. The new fast Mux-D scan flip-flop combines the advantages of the conventional LSSD and Mux-D scan flip-flop, without the disadvantages of each.

    HIGH PERFORMANCE FAST MUX-D SCAN FLIP-FLOP
    6.
    发明申请
    HIGH PERFORMANCE FAST MUX-D SCAN FLIP-FLOP 有权

    公开(公告)号：US20210194469A1

    公开(公告)日：2021-06-24

    申请号：US16726020

    申请日：2019-12-23

    Applicant: Intel Corporation

    Inventor： Amit Agarwal ,  Steven Hsu ,  Simeon Realov ,  Mahesh Kumashikar ,  Ram Krishnamurthy

    IPC: H03K3/037 ,  H03K19/20 ,  H03K3/038 ,  G01R31/3177

    Abstract: A fast Mux-D scan flip-flop is provided, which bypasses a scan multiplexer to a master keeper side path, removing delay overhead of a traditional Mux-D scan topology. The design is compatible with simple scan methodology of Mux-D scan, while preserving smaller area and small number of inputs/outputs. Since scan Mux is not in the forward critical path, circuit topology has similar high performance as level-sensitive scan flip-flop and can be easily converted into bare pass-gate version. The new fast Mux-D scan flip-flop combines the advantages of the conventional LSSD and Mux-D scan flip-flop, without the disadvantages of each.

    HIGH PERFORMANCE FAST MUX-D SCAN FLIP-FLOP
    9.
    发明申请
    HIGH PERFORMANCE FAST MUX-D SCAN FLIP-FLOP 有权

    公开(公告)号：US20220224316A1

    公开(公告)日：2022-07-14

    申请号：US17711638

    申请日：2022-04-01

    Applicant: Intel Corporation

    Inventor： Amit Agarwal ,  Steven Hsu ,  Simeon Realov ,  Mahesh Kumashikar ,  Ram Krishnamurthy

    IPC: H03K3/037 ,  G01R31/3177 ,  H03K3/038 ,  H03K19/20

    Abstract: A fast Mux-D scan flip-flop is provided, which bypasses a scan multiplexer to a master keeper side path, removing delay overhead of a traditional Mux-D scan topology. The design is compatible with simple scan methodology of Mux-D scan, while preserving smaller area and small number of inputs/outputs. Since scan Mux is not in the forward critical path, circuit topology has similar high performance as level-sensitive scan flip-flop and can be easily converted into bare pass-gate version. The new fast Mux-D scan flip-flop combines the advantages of the conventional LSSD and Mux-D scan flip-flop, without the disadvantages of each.

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